e927551827
manual: add highfinesse-net port
2018-11-09 19:39:25 +01:00
14b6b63916
ad9910: rewire io_delay tuning
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This now reliably locates the SYNC_CLK-IO_UPDATE edge by doing two
scans at different delays between start and stop IO_UPDATE.
It also works well when one delay is very close to the edge.
And it correctly identifies which (start or stop) pulse hit or crossed
the SYNC_CLK edge.
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 18:38:27 +00:00
fe3d6661eb
manual: kasli device name for zadig on windows
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 15:00:59 +01:00
38c6878d49
urukul: mention min/max attenuation
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 13:32:05 +01:00
e565ca6b82
urukul: slow down att write to datasheet limit
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 13:23:06 +01:00
998be50f07
urukul: handle MSB in att_reg
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-09 13:21:14 +01:00
David Nadlinger
9740032a94
firmware: Fix dma_record_output_wide
2018-11-08 11:06:43 +00:00
fcb611d1d2
test_ad9910: don't expect large SYNC_IN delay margins
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sinara-hw/Urukul#16
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-07 18:18:35 +01:00
e6efe830c4
ad9910: rewire sync delay tuning
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* search from wide window end
* decouple margins and minimum window size
* add note about kasli jitter
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-07 14:52:03 +00:00
6c00ab57c0
test_ad9910: relax SYNC window
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 19:31:38 +01:00
172633c7da
test_ad9910: default to a useful seed
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 17:35:57 +01:00
0b2661a34d
ad9910: robustify SYNC window finding
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don't integrate too long, find the window tip fast and early
a couple 100 SYNC pulses are sufficient
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 12:41:21 +00:00
ba4bf6e59b
kasli: don't pass rtio pll feedback through bufg
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UG472: "The MMCM performance increases because the
feedback clock is not subjected to noise on the core supply since it
never passes through a block powered by this supply."
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 11:58:55 +00:00
b6e4961b0f
kasli: lower RTIO clock jitter
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* high bandwidth since the si5324 is good
* no low power ibufgds
* drop bufg between ibufgds and pll
* increase pll vco frequency to 1.5 GHz
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 11:43:19 +00:00
e17e458c58
ptb2: add sync to urukul0 for ad9910 usage
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 10:06:51 +00:00
73b7124091
test_ad9910: print sync scan for debugging
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-06 10:04:21 +01:00
9a3d81ffee
kasli: fix tester clk_sel
2018-11-06 14:49:21 +08:00
fb12df7e01
Revert "kasli_tester: urukul0 mmcx clock defunct"
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This reverts commit 68220c316d
2018-11-06 14:33:21 +08:00
31f68ddf6c
Merge branch 'urukul-sync'
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* urukul-sync: (29 commits)
urukul: flake8 [nfc]
ad9910: flake8 [nfc]
urukul/ad9910 test: remove unused import
test_urukul: relax speed
urukul,ad9910: print speed metrics
kasli: add PTB2 (external clock and SYNC)
kasli: add sync to LUH, HUB, Opticlock
kasli_tester: urukul0 mmcx clock defunct
test_ad9910: relax ifc mode read
tests: add Urukul-AD9910 HITL unittests including SYNC
ad9910: add init bit explanation
test: add Urukul CPLD HITL tests
ad9910: fiducial timestamp for tracking phase mode
ad9910: add phase modes
ad9910: fix pll timeout loop
tester: add urukul sync
ptb: back out urukul-sync
ad9910: add IO_UPDATE alignment and tuning
urukul: set up sync_in generator
ad9910: add io_update alignment measurement
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close #1143
2018-11-05 19:54:30 +01:00
6fb18270a2
urukul: flake8 [nfc]
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:45:24 +01:00
832690af9a
ad9910: flake8 [nfc]
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:44:51 +01:00
6d525e2f9a
urukul/ad9910 test: remove unused import
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:40:57 +01:00
36c5a7cd04
test_urukul: relax speed
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works fine at < 3µs here but needs <5 µs on buildbot-kasli-tester
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:20 +01:00
89fecfab50
urukul,ad9910: print speed metrics
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:18 +01:00
32d538f72b
kasli: add PTB2 (external clock and SYNC)
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:16 +01:00
d8a5951a13
kasli: add sync to LUH, HUB, Opticlock
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for #1143 , also add missing LUH device db
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:14 +01:00
68220c316d
kasli_tester: urukul0 mmcx clock defunct
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:11 +01:00
89fadab63d
test_ad9910: relax ifc mode read
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:08 +01:00
f522e211ba
tests: add Urukul-AD9910 HITL unittests including SYNC
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for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:06 +01:00
9fb850ae75
ad9910: add init bit explanation
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:02 +01:00
bc04da15c5
test: add Urukul CPLD HITL tests
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for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:37:00 +01:00
141cc7d99f
ad9910: fiducial timestamp for tracking phase mode
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:58 +01:00
2f6d3f79ff
ad9910: add phase modes
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* simplified and cross-referenced the explanation of the different
phase modes.
* semantically and functionally merged absolute and tracking/coherent
phase modes.
* simplified numerics to calculate phase correction
* added warning about possible inconsistency with DMA and default
phase mode
* restricted __all__ imports
* moved continuous/relative phase offset tracking from an instance
variable to a "handle" returned by set()/set_mu() in order to avoid
state inconsistency with DMA (#1113 #1115 )
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:55 +01:00
d3ad2b7633
ad9910: fix pll timeout loop
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:53 +01:00
4269d5ad5c
tester: add urukul sync
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:52 +01:00
60d3bc63a7
ptb: back out urukul-sync
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... for backwards compatibility.
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:50 +01:00
06139c0f4d
ad9910: add IO_UPDATE alignment and tuning
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for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:48 +01:00
1066430fa8
urukul: set up sync_in generator
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:46 +01:00
4bbd833cfe
ad9910: add io_update alignment measurement
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for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:44 +01:00
7b92282012
ad9910: add docs for sync tuning, refactor
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:42 +01:00
8a47a6b2fb
ad9910: disable sync_clk output
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:40 +01:00
65e2ebf960
ad9910: add sync delay control, auto tuning
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* expose multi device sync functionality
* sync delay configuration interface
* auto-tuning of sync delay from device_db seed
for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:37 +01:00
8dbf5f87fd
ad9910: simplify io_update pulsing on init, set_mu
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:35 +01:00
0b3b07a7da
ad9910: add power down method
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:34 +01:00
3538444876
urukul: add sync_in to eem0-7 name
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:32 +01:00
0433e8f4fe
urukul: add sync_in generator
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for #1143
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:30 +01:00
f62c1ff0bb
TTLClockGen: expose acc_width
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:27 +01:00
f755a4682a
device_db_ptb: fix zotino clr
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Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-11-05 19:36:24 +01:00
David Nadlinger
abad916383
RELEASE_NOTES: Fix typo
2018-11-03 20:33:19 +08:00
David Nadlinger
8b5df9c151
RELEASE_NOTES: TTL timeline cursor API changes
2018-11-03 20:33:19 +08:00
