occheung/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity
8,343 Commits 14 Branches 35 Tags 23 MiB
d5a7755584
Commit Graph

8343 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Sebastien Bourdeauducq
e8fe8409b2 libartiq_support: compatibility with recent stable rustc 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq
cabe5ace8e compiler: remove DebugInfoEmitter for now 
Causes problems with LLVM 9 and not needed at first.
 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq
6629a49e86 compiler: use LLVM binutils/linker for Arm as well 
Previously we kept GNU Binutils because they are less of a pain to support
on Windoze - the source of so many problems - but with RISC-V we need to
update LLVM anyway.
 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq
43d120359d compiler: switch to upstream llvmlite and RISC-V target 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq
5656e52581 remove profiler 2021-09-10 13:25:12 +08:00
occheung
1b8b4baf6a ksupport: fix panic, libc, unwind 2021-09-10 13:25:12 +08:00
occheung
905330b0f1 ksupport: handle riscv exceptions 2021-09-10 13:25:12 +08:00
occheung
50a62b3d42 liballoc: change align to 16 bytes 2021-09-10 13:25:12 +08:00
occheung
7f0bc9f7f0 runtime/makefile: specify emulation, flip endianness 2021-09-10 13:25:12 +08:00
occheung
c42adfe6fd runtime.ld: merge .sbss & .bss 2021-09-10 13:25:12 +08:00
occheung
f56152e72f rust: fix dependencies 2021-09-10 13:25:12 +08:00
occheung
c800b6c8d3 runtime: update rust alloc, managed 2021-09-10 13:25:09 +08:00
occheung
e99061b013 runtime: add riscv 2021-09-10 13:23:22 +08:00
occheung
ecedec577c runtime: impl riscv exception handling 2021-09-10 13:23:15 +08:00
occheung
252594a606 runtime: impl riscv panic handler 2021-09-10 13:20:31 +08:00
occheung
31bf17563c personality: update from rust/panic_unwind 2021-09-10 13:20:31 +08:00
occheung
bfddd8a30f libdyld: add riscv support 2021-09-10 13:20:31 +08:00
occheung
ad3037d0f6 libc: add minimal C types 2021-09-10 13:20:31 +08:00
occheung
daaf6c3401 libunwind: add rust interface 2021-09-10 13:20:31 +08:00
occheung
6d9cebfd42 satman: handle .sbss generation 2021-09-10 13:20:31 +08:00
occheung
96438c9da7 satman: make fbi big-endian 2021-09-10 13:20:31 +08:00
occheung
6535b2f089 satman: fix feature 2021-09-10 13:20:31 +08:00
occheung
45adaa1d98 satman: add riscv exception handling 2021-09-10 13:20:31 +08:00
occheung
869a282410 satman: use riscv 2021-09-10 13:20:31 +08:00
occheung
ebb9f298b5 proto_artiq: update alloc type path 2021-09-10 13:20:31 +08:00
occheung
97a0132f15 libio: update alloc type path 2021-09-10 13:20:31 +08:00
occheung
37ea863004 libio: pin failure version 2021-09-10 13:20:31 +08:00
occheung
3ff74e0693 bootloader: handle .sbss generation in .ld 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung
448fe0e8cf bootloader: fix panic 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung
8294d7fea5 bootloader: swap endianness 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung
13032272fd bootloader: add rv32 exception handler 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung
46102ee737 board_misoc: build vectors.S with rv64 target in misoc 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung
b87ea79d51 rv32: rm irq & vexriscv-rust 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung
9aee42f0f2 rv32/boot: remove hotswap 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
occheung
82b4052cd6 libboard_misoc: vexriscv integration 
Signed-off-by: occheung <dc@m-labs.hk>
 2021-09-10 13:20:31 +08:00
Leon Riesebos
2cf144a60c ddb_template: edge counter keys correspond with according ttl keys 
previously ttl_counter_0 and ttl_0 could be on completely different physical ttl output channels
with this change, ttl_0_counter (note the changed key format) is always on the same channel as ttl_0

Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
 2021-09-06 09:06:04 +08:00
Robert Jördens
e7a46ec767
Merge pull request #1749 from airwoodix/phaser-frame-alignment-utils 
Phaser: add helpers to align updates with RTIO timeline
 2021-09-03 14:00:17 +02:00
Etienne Wodey
4d7bd3ee32 phaser: fail init() if frame timestamp measurement times out 
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
 2021-09-03 12:01:26 +02:00
Etienne Wodey
075cb26dd7 phaser: rename get_next_frame_timestamp() to get_next_frame_mu() 
and implement review comments (PR #1749)

Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
 2021-09-03 09:58:01 +02:00
Etienne Wodey
7aebf02f84 phaser: docs: add reference to get_next_frame_timestamps(), fix typo 
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
 2021-09-01 17:44:46 +02:00
Etienne Wodey
61b44d40dd phaser: add labels to debug init prints 
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
 2021-09-01 17:43:30 +02:00
Etienne Wodey
65f8a97b56 phaser: add helpers to align updates to the RTIO timeline 
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
 2021-09-01 17:42:54 +02:00
Robert Jördens
11790c6d7c
Merge pull request #1746 from quartiq/suservo_tester 
Suservo tester
 2021-08-19 10:20:29 +02:00
SingularitySurfer
65f63e6927 fix suservo start 2021-08-19 07:38:48 +00:00
Robert Jördens
a53162d01d tester: tweak suservo 
* p gain 1 to get reasonable power
* refine testing instructions and comments
 2021-08-19 09:17:14 +02:00
SingularitySurfer
4d21a72407 Implement SUServo tester. 2021-08-18 15:10:27 +00:00
Mikołaj Sowiński
898122f3e5
Added support for HVAMP_8CH (#1741) 2021-08-16 13:39:00 +08:00
Sebastien Bourdeauducq
420891ba54 syntax 2021-08-12 13:01:35 +08:00
Sebastien Bourdeauducq
9f94bc61ae missing part of 477b1516d 2021-08-12 12:55:37 +08:00
Sebastien Bourdeauducq
c69a1316ad compiler: stop using sys.version_info for parser 2021-08-12 12:52:24 +08:00