whitequark
abf2b32b20
coredevice.dds: work around the round(numpy.float64()) snafu.
2016-11-20 09:49:58 +00:00
whitequark
d7f4397924
coredevice.dds: update from obsolete int(width=) syntax ( fixes #621 ).
2016-11-20 09:49:39 +00:00
David Leibrandt
4a62e09bd4
gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623
2016-11-20 15:22:32 +08:00
12e39a64cf
sawg: reduce f0 oscillator width to 32
2016-11-19 17:07:07 +01:00
04813ea29b
sawg: wir up limiting, saturating addition
2016-11-19 16:12:27 +01:00
e53d0bcd5b
dsp: add limits support to SatAddMixin
2016-11-19 16:12:27 +01:00
97a54046e8
rtio: auto clear output event data and address
...
This is to support channels where variable length
event data is well-defined through zero-padding.
E.g. in the case of `Spline` zero-padding of events naturally
corresponds to low-order knots.
Use timestamp change as trigger. This assumes that writes to the
timestamp register always precede address and data writes.
It does not break support for ganged writes of the same event
timestamp and data/address to multiple channels or
channel-addresses.
2016-11-19 16:12:27 +01:00
b714137f76
phaser: 150 MHz rtio/jesd clock
2016-11-19 13:16:30 +01:00
02adae7397
drtio: fix link shutdown
2016-11-19 11:01:33 +08:00
abd1b2a94e
drtio: wait longer for remote (bruteforce clock aligner can be slow)
2016-11-19 11:01:09 +08:00
381e58434f
drtio: handle link restarts at transceiver level
2016-11-19 10:46:56 +08:00
0ee47e77ae
phaser: fix widths
2016-11-18 17:24:11 +01:00
bcde26f990
Revert "phaser: cap phy data width to 64 temporarily"
...
This reverts commit 342b9e977e
2016-11-18 17:08:44 +01:00
641f07119f
runtime: support rtio data wider than 64 bit
2016-11-18 17:08:33 +01:00
ba94ed8f4b
drtio: check for absence of disparity errors before claiming RX ready
2016-11-19 00:05:59 +08:00
342b9e977e
phaser: cap phy data width to 64 temporarily
2016-11-18 15:46:59 +01:00
7664b226f2
phaser/conda: bump jesd204b
2016-11-18 15:34:03 +01:00
14ddcd2e30
Revert "dsp/Delay: reset_less"
...
for now
This reverts commit 98193d6fa1
2016-11-18 15:25:42 +01:00
d678bb3fb6
phaser: update sawg tests
2016-11-18 15:23:56 +01:00
whitequark
2015fe9de0
doc: update installing_from_source for LLVM 3.9 transitionl
2016-11-18 10:35:36 +00:00
4d07974a34
drtio: reset link from CPU
2016-11-18 17:45:33 +08:00
f040e27041
drtio: add timeout on FIFO get space request
2016-11-18 17:44:48 +08:00
whitequark
c7844d5223
runtime: use proper format for git commit.
...
Fixes #620 .
2016-11-17 15:20:21 +00:00
bb047aabe9
drtio: simpler link layer
2016-11-17 22:32:39 +08:00
51f23feeac
dsp: implement sawg features
2016-11-17 03:20:37 +01:00
98193d6fa1
dsp/Delay: reset_less
2016-11-17 02:36:29 +01:00
424a1f8f4e
dsp: move test tools
2016-11-16 13:39:19 +01:00
09363e1da8
drtio: aux controller unittest
2016-11-16 19:45:28 +08:00
140bb0ecee
drtio: aux controller fixes
2016-11-16 19:44:03 +08:00
7fa9a4efc3
drtio: aux controller unittest WIP
2016-11-15 12:02:53 +08:00
6c9965b444
drtio: aux controller fixes
2016-11-15 12:02:41 +08:00
e1394db861
drtio: aux controller minor fixes
2016-11-14 17:26:30 +08:00
84bd962ed5
drtio: integrate aux controller
2016-11-14 17:20:47 +08:00
a4d92716da
drtio: fix aux receiver, add aux transmitter
2016-11-14 17:18:54 +08:00
b9ce2bb1f0
Merge branch 'phaser' into phaser2
...
* phaser: (127 commits)
phaser: use misoc cordic
phaser: fix DDS dummy cfg
runtime: disable the Nagle algorithm entirely.
runtime: buffer RPC send packets.
runtime: don't print debug messages to the UART.
runtime: print microsecond timestamps in debug messages.
artiq_devtool: abort if build failed.
conda: bump llvmlite-artiq dep.
conda: bump llvmlite-artiq dep.
llvm_ir_generator: use !{→unconditionally.}invariant.load metadata.
artiq_devtool: more robust port forwarding.
setup: remove paramiko dependency (optional and developer-only)
artiq_devtool: implement.
artiq_compile: actually disable attribute writeback.
conda: use pythonparser 1.0.
conda: tighten pythonparser dependency (fixes #600 ).
doc: clarify kernel_invariant doc (fixes #609 ).
compiler: Emit all-kernel_invariant objects as LLVM constants
conda: update for LLVM 3.9.
add has_dds, use config flags
...
2016-11-13 17:30:37 +01:00
70a70320bd
phaser: use misoc cordic
2016-11-13 17:29:38 +01:00
2e482505c6
phaser: fix DDS dummy cfg
2016-11-13 17:08:59 +01:00
f2f131e0fb
drtio: add aux receiver (untested)
2016-11-14 00:04:53 +08:00
aedb6747f2
Merge branch 'master' into phaser
...
* master: (47 commits)
runtime: disable the Nagle algorithm entirely.
runtime: buffer RPC send packets.
runtime: don't print debug messages to the UART.
runtime: print microsecond timestamps in debug messages.
artiq_devtool: abort if build failed.
conda: bump llvmlite-artiq dep.
conda: bump llvmlite-artiq dep.
llvm_ir_generator: use !{→unconditionally.}invariant.load metadata.
artiq_devtool: more robust port forwarding.
setup: remove paramiko dependency (optional and developer-only)
artiq_devtool: implement.
artiq_compile: actually disable attribute writeback.
conda: use pythonparser 1.0.
conda: tighten pythonparser dependency (fixes #600 ).
doc: clarify kernel_invariant doc (fixes #609 ).
compiler: Emit all-kernel_invariant objects as LLVM constants
conda: update for LLVM 3.9.
add has_dds, use config flags
Revert "Revert "Revert "Revert "Update for LLVM 3.9.""""
Revert "Revert "Revert "Update for LLVM 3.9."""
...
2016-11-13 16:54:28 +01:00
whitequark
18c394976e
runtime: disable the Nagle algorithm entirely.
...
See also commit feed91d; that commit fixed the test_rpc_timing test,
but caused frequent hangs elsewhere, which were also caused by buggy
Nagle implementation. Just disable this entirely, as with our
explicit buffering it provides no benefit anyway.
2016-11-13 00:33:24 +00:00
whitequark
feed91d8b2
runtime: buffer RPC send packets.
...
This brings mean RPC time from ~45ms to ~2ms.
The cause of the slowness without buffering is, primarily, that lwip
is severely pessimized by small writes, whether with Nagle on or off.
(In fact, disabling Nagle makes it function *better* on many small
writes, which begs the question of what's the point of having Nagle
there in the first place.) In practical terms, the slowness appears
only when writing a 4-byte buffer (the synchronization segment);
writing buffers of other sizes does not trigger the problem.
This all is extremely confusing and the fix is partly palliative,
but since it seems to work reliably and we're migrating off lwip
I think it is unwise to spend any more time debugging this.
2016-11-12 23:06:33 +00:00
whitequark
3ce1826891
runtime: don't print debug messages to the UART.
...
It takes ~4ms to print an empty log line because of how slow
the UART is. This makes the log timestamps useless for debugging
performance problems.
After this commit, it takes ~75us to print an empty log line instead,
which pessimizes test_rpc_timing by less than 2ms with tracing
enabled.
2016-11-12 20:26:32 +00:00
whitequark
acc5e53b32
runtime: print microsecond timestamps in debug messages.
2016-11-12 20:26:32 +00:00
whitequark
dca3fb5c96
artiq_devtool: abort if build failed.
2016-11-12 20:26:32 +00:00
whitequark
7c2b1155ef
conda: bump llvmlite-artiq dep.
2016-11-12 13:58:00 +00:00
whitequark
5eb940deb7
conda: bump llvmlite-artiq dep.
2016-11-12 04:09:34 +00:00
whitequark
d3ee858d16
llvm_ir_generator: use !{→unconditionally.}invariant.load metadata.
...
This helps LICM, among other things.
2016-11-12 04:08:58 +00:00
whitequark
8b6418c604
artiq_devtool: more robust port forwarding.
2016-11-11 15:22:07 +00:00
fbc2420443
setup: remove paramiko dependency (optional and developer-only)
2016-11-11 11:05:37 +08:00
whitequark
3b6cbb1f06
artiq_devtool: implement.
2016-11-10 20:25:15 +00:00
