b30ed75e69
kernel.ld: load elf header and prog headers
...
ld.lld has a habit of not putting the headers under any load sections.
However, the headers are needed by libunwind to handle exception raised by the kernel.
Creating PT_LOAD section with FILEHDR and PHDRS solves this issue. Other PHDRS are also specified as linkers (not limited to ld.lld) will not create additional unspecified headers even when necessary.
2021-09-10 13:25:12 +08:00
279593f984
ksupport.ld: merge sbss with bss
2021-09-10 13:25:12 +08:00
1ba8c8dfee
runtime: remove irq again
2021-09-10 13:25:12 +08:00
942bd1a95d
flake: add hydraJobs
2021-09-10 13:25:12 +08:00
3d629006df
makefiles: revert byte-swaps
2021-09-10 13:25:12 +08:00
7542105f0f
board_misoc: remove pcr
...
VexRiscv seems to not support additional hardware performance counter, at least I have not seen any documentation on how to use it.
2021-09-10 13:25:12 +08:00
01ca114c66
runtime: remove irq dependency
2021-09-10 13:25:12 +08:00
36171f2c61
runtime: remove inaccurate sp on panic
2021-09-10 13:25:12 +08:00
01e357e5d3
ksupport.ld: reduce load section alignment
2021-09-10 13:25:12 +08:00
f77b607b56
compiler: generate symbols
2021-09-10 13:25:12 +08:00
1293e0750e
ld, makefiles: use ld.lld
2021-09-10 13:25:12 +08:00
fc42d053d9
kernel: use vexriscv
2021-09-10 13:25:12 +08:00
9adab6c817
flake: add devshell
2021-09-10 13:25:12 +08:00
8c468d0346
flake: switch to nightly rust with mozilla overlay
2021-09-10 13:25:12 +08:00
1b516b16e2
targets: default to vexriscv cpu
2021-09-10 13:25:12 +08:00
be5ae5c5b4
flake: configure binary cache
2021-09-10 13:25:12 +08:00
d13efd6587
add Nix flake
2021-09-10 13:25:12 +08:00
e8fe8409b2
libartiq_support: compatibility with recent stable rustc
2021-09-10 13:25:12 +08:00
cabe5ace8e
compiler: remove DebugInfoEmitter for now
...
Causes problems with LLVM 9 and not needed at first.
2021-09-10 13:25:12 +08:00
6629a49e86
compiler: use LLVM binutils/linker for Arm as well
...
Previously we kept GNU Binutils because they are less of a pain to support
on Windoze - the source of so many problems - but with RISC-V we need to
update LLVM anyway.
2021-09-10 13:25:12 +08:00
43d120359d
compiler: switch to upstream llvmlite and RISC-V target
2021-09-10 13:25:12 +08:00
5656e52581
remove profiler
2021-09-10 13:25:12 +08:00
1b8b4baf6a
ksupport: fix panic, libc, unwind
2021-09-10 13:25:12 +08:00
905330b0f1
ksupport: handle riscv exceptions
2021-09-10 13:25:12 +08:00
50a62b3d42
liballoc: change align to 16 bytes
2021-09-10 13:25:12 +08:00
7f0bc9f7f0
runtime/makefile: specify emulation, flip endianness
2021-09-10 13:25:12 +08:00
c42adfe6fd
runtime.ld: merge .sbss & .bss
2021-09-10 13:25:12 +08:00
f56152e72f
rust: fix dependencies
2021-09-10 13:25:12 +08:00
c800b6c8d3
runtime: update rust alloc, managed
2021-09-10 13:25:09 +08:00
e99061b013
runtime: add riscv
2021-09-10 13:23:22 +08:00
ecedec577c
runtime: impl riscv exception handling
2021-09-10 13:23:15 +08:00
252594a606
runtime: impl riscv panic handler
2021-09-10 13:20:31 +08:00
31bf17563c
personality: update from rust/panic_unwind
2021-09-10 13:20:31 +08:00
bfddd8a30f
libdyld: add riscv support
2021-09-10 13:20:31 +08:00
ad3037d0f6
libc: add minimal C types
2021-09-10 13:20:31 +08:00
daaf6c3401
libunwind: add rust interface
2021-09-10 13:20:31 +08:00
6d9cebfd42
satman: handle .sbss generation
2021-09-10 13:20:31 +08:00
96438c9da7
satman: make fbi big-endian
2021-09-10 13:20:31 +08:00
6535b2f089
satman: fix feature
2021-09-10 13:20:31 +08:00
45adaa1d98
satman: add riscv exception handling
2021-09-10 13:20:31 +08:00
869a282410
satman: use riscv
2021-09-10 13:20:31 +08:00
ebb9f298b5
proto_artiq: update alloc type path
2021-09-10 13:20:31 +08:00
97a0132f15
libio: update alloc type path
2021-09-10 13:20:31 +08:00
37ea863004
libio: pin failure version
2021-09-10 13:20:31 +08:00
3ff74e0693
bootloader: handle .sbss generation in .ld
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
448fe0e8cf
bootloader: fix panic
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
8294d7fea5
bootloader: swap endianness
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
13032272fd
bootloader: add rv32 exception handler
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
46102ee737
board_misoc: build vectors.S with rv64 target in misoc
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
b87ea79d51
rv32: rm irq & vexriscv-rust
...
Signed-off-by: occheung <dc@m-labs.hk>
2021-09-10 13:20:31 +08:00
