471605ec1e
pdq: move to https://github.com/m-labs/pdq
2017-07-19 17:35:28 +02:00
5c66b63768
setup.py etc: update license
2017-07-18 11:31:43 +02:00
377c776ec8
examples/dma_blink: replay → playback
2017-07-18 14:01:08 +08:00
9898681a38
aqctl_corelog: only set logging.DEBUG after the server is set up
...
Otherwise asyncio pollutes the log.
2017-07-18 14:00:06 +08:00
whitequark
dd87508a7f
Implement forwarding of logs from core device to master.
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Fixes #691 .
2017-07-18 05:31:59 +00:00
whitequark
819440f839
runtime: split log timestamp into secs.micros.
2017-07-18 05:31:59 +00:00
whitequark
9e38132c0a
artiq_devtool: don't drop data in unpredictable ways (sigh).
2017-07-18 05:31:59 +00:00
a201a9abd9
drtio: multilink transceiver interface
2017-07-18 13:27:33 +08:00
d96c2abe44
pdq: read/write_reg -> get/set_reg
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see also m-labs/pdq#14
2017-07-17 21:45:46 +02:00
9045b4cc19
drtio: initial firmware support for multi-link
2017-07-18 00:40:21 +08:00
94ee48860a
doc: fix phaser channel number statement
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closes #781
2017-07-15 20:24:50 +02:00
whitequark
d06d53b00d
firmware: don't bail out if building not from a git checkout ( #783 ).
2017-07-15 03:16:21 +00:00
0253db0421
conda: fix misoc git hash
2017-07-13 19:32:03 +08:00
4deb5f6a45
gateware: use new MiSoC Wishbone address system
2017-07-13 19:16:49 +08:00
mntng
40ca951750
kc705: add SPI bus for memory card
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This will be useful for SPI unit tests using a SD card as victim.
2017-07-12 00:27:44 +08:00
298ceafd92
README_PHASER: fix ref_multiplier
2017-07-08 19:44:57 +02:00
f0841f5489
spline: be really verbose
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closes #773
2017-07-07 11:43:58 +02:00
7b130a2c32
sawg: confirm smooth(order=3)
2017-07-07 11:36:03 +02:00
3bc0e32dc0
sawg: advance the timeline on Config access
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c.f. #773 #765
2017-07-07 11:33:58 +02:00
3222f5036f
sawg: describe latency matching in detail
2017-07-06 10:06:21 +02:00
whitequark
1e2603572a
runtime: fix a bug causing sockets to get stuck in CLOSE-WAIT.
2017-07-05 16:27:36 +00:00
whitequark
86c027e9c5
artiq_flash: don't require binaries to merely restart FPGA.
2017-07-04 18:55:38 +00:00
whitequark
ee1d5dbccb
runtime: allow a much larger log buffer and avoid hacks.
2017-07-04 18:18:31 +00:00
whitequark
3ab8a4d505
aqctl_corelog: add missing script definition to setup.py.
2017-07-04 18:04:25 +00:00
whitequark
7a5fbc1622
devtool: forward port 1383 (moninj).
2017-07-04 17:54:18 +00:00
whitequark
4e5ea1bbaf
dashboard: fix a crash touching moninj without a connection.
2017-07-04 17:53:48 +00:00
2f1029c292
Revert "sawg: advance dds 1/2 by one sample group"
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This reverts commit 8e0a1cbdc8#772
The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.
2017-07-04 17:55:19 +02:00
8e0a1cbdc8
sawg: advance dds 1/2 by one sample group
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closes #772
2017-07-04 16:51:58 +02:00
91ca9fbcad
sawg: also give offset some headroom
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closes #771
2017-07-04 16:50:06 +02:00
60809d1cb4
conda: bump misoc (migen change)
2017-07-04 11:58:12 +02:00
78d1f0fdf6
sawg: fix PhasedAccu resets
2017-07-04 11:56:21 +02:00
Florent Kermarrec
42476c64a7
conda: bump migen (Record.connect leave_out --> keep/omit)
2017-07-04 11:26:57 +02:00
Florent Kermarrec
2910b1be5e
artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect
2017-07-04 10:48:06 +02:00
5b26e5de6c
conda: bump migen (reset_less cdc)
2017-07-02 15:41:58 +02:00
d7ad72efa2
doc: point to artiq_flash hardware selection options when writing flash storage. Closes #766
2017-07-02 10:40:52 +08:00
838127d914
rtio: break DMA timing path
2017-07-02 10:24:01 +08:00
whitequark
ea7549cfa4
compiler: coerce while condition to bool.
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Fixes #768 .
2017-07-01 18:59:07 +00:00
911ee4a959
rtio: make pipelined logic reset_less
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* latency-corrected counters
* registered error logic
2017-06-29 12:55:32 +02:00
600a48ac61
dsp.fir: cleanup
2017-06-29 12:18:48 +02:00
dca662a743
dsp.fir: pipeline final systolic adder
2017-06-29 11:33:19 +02:00
32a33500c8
dsp.fir: actively cull zero delays
2017-06-29 11:24:56 +02:00
f520d4a768
rtio: undo _RelaxedAsyncResetSynchronizer
2017-06-28 22:08:15 +02:00
6fad15c532
conda: bump migen, misoc
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* reset_less Cordic
* Signal.like() inherits more
* address decoder changes
2017-06-28 20:56:43 +02:00
3cbbcdfe96
sawg: don't enable_replace for Config
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closes #762
2017-06-28 20:31:40 +02:00
f2632e0fd1
sawg: adapt latency to fir changes
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closes #748
2017-06-28 20:12:30 +02:00
e7db2c6578
dsp.accu: reset_less outputs
2017-06-28 20:04:58 +02:00
6bb994228f
dsp.fir: drop x shift
2017-06-28 19:55:15 +02:00
01847271c5
rtio: use reset_less signal for reset fanout
2017-06-28 19:43:55 +02:00
b9859cc0c3
dsp.fir: remove old/wrong comment
2017-06-28 19:21:57 +02:00
55b5b87490
fir: simplify latency compensation
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Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.
2017-06-28 19:13:43 +02:00
