gateware: use new MiSoC Wishbone address system

artiq/gateware/amp/kernel_cpu.py

@@ -2,7 +2,7 @@ from migen import *
 from misoc.interconnect.csr import *
 from misoc.interconnect import wishbone
 from misoc.cores import mor1kx
-from misoc.integration.soc_core import mem_decoder
+from misoc.integration.wb_slaves import WishboneSlaveManager
 
 
 class KernelCPU(Module):
@@ -14,7 +14,7 @@ class KernelCPU(Module):
 
         # # #
 
-        self._wb_slaves = []
+        self._wb_slaves = WishboneSlaveManager(0x80000000)
 
         # CPU core
         self.clock_domains.cd_sys_kernel = ClockDomain()
@@ -31,16 +31,17 @@ class KernelCPU(Module):
 
         # DRAM access
         self.wb_sdram = wishbone.Interface()
-        self.add_wb_slave(mem_decoder(main_mem_origin), self.wb_sdram)
+        self.add_wb_slave(main_mem_origin, 0x10000000, self.wb_sdram)
 
     def get_csrs(self):
         return [self._reset]
 
     def do_finalize(self):
         self.submodules.wishbonecon = wishbone.InterconnectShared(
-            [self.cpu.ibus, self.cpu.dbus], self._wb_slaves, register=True)
+            [self.cpu.ibus, self.cpu.dbus],
+            self._wb_slaves.get_interconnect_slaves(), register=True)
 
-    def add_wb_slave(self, address_decoder, interface):
+    def add_wb_slave(self, origin, length, interface):
         if self.finalized:
             raise FinalizeError
-        self._wb_slaves.append((address_decoder, interface))
+        self._wb_slaves.add(origin, length, interface)

artiq/gateware/amp/soc.py

@@ -1,6 +1,5 @@
 import os
 
-from misoc.integration.soc_core import mem_decoder
 from misoc.cores import timer
 from misoc.interconnect import wishbone
 from misoc.integration.builder import *
@@ -23,21 +22,22 @@ class AMPSoC:
         self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
         self.csr_devices.append("kernel_cpu")
 
-        self.submodules.mailbox = Mailbox(size=3)
-        self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
+        mailbox_size = 3
+        self.submodules.mailbox = Mailbox(mailbox_size)
+        self.add_wb_slave(self.mem_map["mailbox"], 4*mailbox_size,
                           self.mailbox.i1)
-        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
+        self.kernel_cpu.add_wb_slave(self.mem_map["mailbox"], 4*mailbox_size,
                                      self.mailbox.i2)
         self.add_memory_region("mailbox",
-                               self.mem_map["mailbox"] | 0x80000000, 4)
+                               self.mem_map["mailbox"] | 0x80000000,
+                               4*mailbox_size)
 
     def register_kernel_cpu_csrdevice(self, name, csrs=None):
         if csrs is None:
             csrs = getattr(self, name).get_csrs()
         bank = wishbone.CSRBank(csrs)
         self.submodules += bank
-        self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map[name]),
-                                     bank.bus)
+        self.kernel_cpu.add_wb_slave(self.mem_map[name], 4*2**bank.decode_bits, bank.bus)
         self.add_csr_region(name,
                             self.mem_map[name] | 0x80000000, 32,
                             csrs)

artiq/gateware/targets/kc705_drtio_master.py

@@ -7,7 +7,6 @@ from migen.build.generic_platform import *
 
 from misoc.cores import spi as spi_csr
 from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
-from misoc.integration.soc_core import mem_decoder
 from misoc.integration.builder import builder_args, builder_argdict
 
 from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
@@ -56,7 +55,7 @@ class Master(MiniSoC, AMPSoC):
 
         self.submodules.drtio = DRTIOMaster(self.transceiver)
         self.csr_devices.append("drtio")
-        self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]),
+        self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
                           self.drtio.aux_controller.bus)
         self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
 

artiq/gateware/targets/kc705_drtio_satellite.py

@@ -6,7 +6,6 @@ from migen.build.generic_platform import *
 from misoc.cores import spi as spi_csr
 from misoc.cores import gpio
 from misoc.integration.builder import *
-from misoc.integration.soc_core import mem_decoder
 from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict
 
 from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
@@ -61,7 +60,7 @@ class Satellite(BaseSoC):
             self.transceiver, rtio_channels, self.rx_synchronizer)
         self.csr_devices.append("rx_synchronizer")
         self.csr_devices.append("drtio")
-        self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]),
+        self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
                           self.drtio.aux_controller.bus)
         self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
 

conda/artiq-dev/meta.yaml

@@ -15,7 +15,7 @@ requirements:
     - python >=3.5.3,<3.6
     - setuptools 33.1.1
     - migen 0.5.dev py_117+gite826cb9
-    - misoc 0.6.dev py_22+gite205c2ea
+    - misoc 0.6.dev py_32+git207a8d66
     - jesd204b 0.3
     - binutils-or1k-linux >=2.27
     - llvm-or1k