Commit Graph

2713 Commits

Author SHA1 Message Date
whitequark
b0185f3917 Add profiling to the performance testbench. 2015-07-29 22:23:22 +03:00
whitequark
d7f9af4bb5 Fix accidentally quadratic code in compiler.ir.Function._add_name. 2015-07-29 21:36:31 +03:00
whitequark
6d8d0ff3f5 Update performance testbench to include time spent in ARTIQ. 2015-07-29 21:28:07 +03:00
whitequark
3b5d3e2b1a Add a performance measurement testbench. 2015-07-29 21:17:52 +03:00
55708e8678 pipistrello: drop bitgen_opt change (done upstream) 2015-07-29 11:45:15 -06:00
whitequark
e8c107925c Implement shared object linking. 2015-07-29 20:35:16 +03:00
6b98f867de import DDS phase modes at the top level 2015-07-29 23:32:33 +08:00
1ddb19277f add speed benchmark 2015-07-29 23:29:26 +08:00
86fef7b53b master: do not scan experiments starting with '_' 2015-07-29 23:29:07 +08:00
a8c13cb7de gui: fix NumberEntry min/max 2015-07-29 23:28:34 +08:00
1d34c06d79 rtio: detect collision errors 2015-07-29 19:43:35 +08:00
b548d50a2f test/coredevice: use ttl_out for PulseRate (loop is less available) 2015-07-29 19:42:43 +08:00
whitequark
2cd25f85bf Rename artiq.compiler.testbench.{module → signature}. 2015-07-29 14:32:34 +03:00
whitequark
3378dd57b8 Fold llvmlite patches into m-labs/llvmlite repository. 2015-07-29 13:54:00 +03:00
whitequark
fd46d8b11e Merge branch 'master' into new-py2llvm 2015-07-29 12:52:19 +03:00
whitequark
c40ae9dbd3 MiSoC is not built with -fPIC anymore, remove support code for that. 2015-07-29 12:40:46 +03:00
ebbbdcf194 examples/tdr: cleanup 2015-07-28 23:30:26 -06:00
278570faf6 examples: add TDR toy example 2015-07-28 21:36:10 -06:00
90368415a6 ttl: remove timestamp function
The general idea is that functions that work with absolute timestamps exist only in machine units versions, to help prevent floating point losses of precision. Time differences should be computed in machine units and then converted, e.g. mu_to_seconds(t2-t1).

This function would have had problems after ~50 days of running the device.
2015-07-29 11:11:16 +08:00
2640a57af3 test/coredevice: let output() settle longer 2015-07-28 16:20:05 -06:00
5f5227f01f ttl: add timestamp() 2015-07-28 16:20:05 -06:00
e95b66f114 ttl: remove spurious _mu 2015-07-28 16:20:05 -06:00
whitequark
b179430f6b Specify correct llvmlite branch in installation instructions. 2015-07-28 23:43:07 +03:00
67715f0d2e pipistrello: only put serdes on the lower ttls
this setup is getting a bit power hungry.

pmt0, 1 (rtio channels 0, 1): 4x in and out
ttl0, 1 (rtio channels 2, 3): 4x out
ttl2 (rtio channel 4): 8x out
2015-07-28 12:54:31 -06:00
fb339d294e serdes_s6: no need to reset 2015-07-28 12:54:31 -06:00
9dfbf07743 pipistrello: use 4x serdes for rtio ttl
pipistrello: do not wait for lock on startup

LCK_cycle:6 was added in 6a412f796e1 (mibuild). It waits for _all_
DCM and PLLs to lock (probably irrespective of STARTUP_WAIT).
2015-07-28 12:54:27 -06:00
8e391e2661 kc705: generate 10MHz clock on GPIO SMA
For SynthNV and input tests.
2015-07-28 18:56:47 +08:00
1809a70f5c Revert "pipistrello: use 4x serdes for rtio ttl"
This reverts commit 8e92cc91f5.

Broken. Will revisit.
2015-07-27 23:39:35 -06:00
f0a7078336 Revert "rtiocrg.c: pipistrello also has pll_reset"
This reverts commit bdee914828.
2015-07-27 22:18:45 -06:00
bdee914828 rtiocrg.c: pipistrello also has pll_reset 2015-07-27 22:14:42 -06:00
e95b06e96d pipistrello: tie unused dds.p low 2015-07-27 21:48:56 -06:00
8e92cc91f5 pipistrello: use 4x serdes for rtio ttl 2015-07-27 21:29:50 -06:00
9ac5bc52d4 rtio: add spartan6 serdes, 4x and 8x 2015-07-27 21:01:15 -06:00
ae3a52c49c runtime: fix KERNELCPU_PAYLOAD_ADDRESS 2015-07-28 02:12:14 +08:00
whitequark
eec4a2d2d2 Update buildsystem to track -fPIC and ranlib removal in MiSoC. 2015-07-27 21:10:46 +03:00
0cd74533ca runtime: more explicit message about startup clock failure 2015-07-28 00:38:38 +08:00
228f7c3d61 manual: update xc3sprog download 2015-07-28 00:38:20 +08:00
7feaca7c7c runtime: allow selecting external clock at startup 2015-07-28 00:19:07 +08:00
09d837e4ba runtime: monitor RTIO clock status 2015-07-28 00:05:24 +08:00
299bc1cb7e kc705: output divided-by-2 RTIO clock 2015-07-27 20:46:44 +08:00
256e99f0d7 kc705: crg cleanup 2015-07-27 20:31:37 +08:00
2a95e866aa kc705: use 8X SERDES RTIO PHY 2015-07-27 20:12:17 +08:00
fe57308e71 runtime: support for RTIO PLL 2015-07-27 20:11:31 +08:00
whitequark
244ace19e1 Add artiq_raise_from_c macro. 2015-07-27 13:56:18 +03:00
whitequark
edffb40ef2 On uncaught exception, execute finally clauses and collect backtrace. 2015-07-27 13:51:24 +03:00
whitequark
2939d4f0f3 Add tests for finally clause and reraising. 2015-07-27 12:36:21 +03:00
whitequark
a83e7e2248 Add tests for exceptional control flow. 2015-07-27 10:22:28 +03:00
whitequark
90be44c596 Add tests for non-exceptional control flow across finally. 2015-07-27 10:13:22 +03:00
whitequark
7c77dd317a Implement __artiq_personality. 2015-07-27 09:10:20 +03:00
d7138b25f2 examples/ddb: add device aliases for unittests 2015-07-27 12:22:56 +08:00