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c591f1a74d
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targets/ARTIQMiniSoC: support dynamic switching of RTIO clock to XTRIG
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2014-12-01 18:53:29 +08:00 |
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99d530e498
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targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA
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2014-12-01 17:31:35 +08:00 |
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1f6441948d
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more TTL channels and larger input FIFOs on Papilio Pro
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2014-11-30 15:50:57 +08:00 |
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8d59f843fb
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doc/manual: add FPGA board info and TTL line assignments
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2014-11-21 16:39:22 -08:00 |
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