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doc/manual: add FPGA board info and TTL line assignments

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Sebastien Bourdeauducq 2014-11-21 16:39:22 -08:00
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doc/manual/fpga_board_ports.rst Normal file
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FPGA board ports
================
KC705
-----
The main target board for the ARTIQ core device is the KC705 development board from Xilinx.
Papilio Pro
-----------
The low-cost Papilio Pro FPGA board can be used with some limitations.
When plugged to a QC-DAQ LVDS adapter, the AD9858 DDS hardware can be used in addition to a limited number of TTL channels. The TTL lines are mapped to RTIO channels as follows:
+--------------+----------+----------------+
| RTIO channel | TTL line | Capability |
+==============+==========+================+
| 0 | PMT0 | Output + input |
+--------------+----------+----------------+
| 1 | TTL0 | Output only |
+--------------+----------+----------------+
| 2 | TTL1 | Output only |
+--------------+----------+----------------+
| 3 | TTL2 | Output only |
+--------------+----------+----------------+