2f838e3512
rtio: fix i_data/o_data csr endianess
2016-11-21 12:15:26 +01:00
174c4be218
phaser: false paths sys<->{jesd,phy.tx}
2016-11-21 09:57:33 +01:00
whitequark
3485c83429
Fix tests.
2016-11-21 06:40:47 +00:00
whitequark
009d396740
Move mu_to_seconds, seconds_to_mu to Core.
2016-11-21 05:37:30 +00:00
whitequark
06ea76336d
artiq_devtool: don't crash on invalid utf-8.
2016-11-21 05:37:27 +00:00
whitequark
b562b0fbc4
artiq_devtool: detect a race condition during connect.
2016-11-21 03:10:41 +00:00
whitequark
7af41bd29c
llvm_ir_generator: handle no-op coercions.
2016-11-21 02:25:34 +00:00
9221a275cb
sawg: kernel support (wip)
2016-11-20 16:39:53 +01:00
74e5013fe5
sawg: fix b delay width
2016-11-20 16:39:22 +01:00
eb18466820
conda: use development version of migen/misoc
2016-11-20 22:56:48 +08:00
whitequark
cdb29f9caa
Revert accidentally committed code.
2016-11-20 14:32:59 +00:00
ad1049d59a
Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 "
...
This reverts commit 4a62e09bd4
2016-11-20 21:35:07 +08:00
whitequark
f5cca6b09e
analyses.invariant_detection: implement ( #622 ).
2016-11-20 12:48:26 +00:00
whitequark
30598720f4
Fix whitespace.
2016-11-20 09:50:00 +00:00
whitequark
abf2b32b20
coredevice.dds: work around the round(numpy.float64()) snafu.
2016-11-20 09:49:58 +00:00
whitequark
d7f4397924
coredevice.dds: update from obsolete int(width=) syntax ( fixes #621 ).
2016-11-20 09:49:39 +00:00
David Leibrandt
4a62e09bd4
gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623
2016-11-20 15:22:32 +08:00
12e39a64cf
sawg: reduce f0 oscillator width to 32
2016-11-19 17:07:07 +01:00
04813ea29b
sawg: wir up limiting, saturating addition
2016-11-19 16:12:27 +01:00
e53d0bcd5b
dsp: add limits support to SatAddMixin
2016-11-19 16:12:27 +01:00
97a54046e8
rtio: auto clear output event data and address
...
This is to support channels where variable length
event data is well-defined through zero-padding.
E.g. in the case of `Spline` zero-padding of events naturally
corresponds to low-order knots.
Use timestamp change as trigger. This assumes that writes to the
timestamp register always precede address and data writes.
It does not break support for ganged writes of the same event
timestamp and data/address to multiple channels or
channel-addresses.
2016-11-19 16:12:27 +01:00
b714137f76
phaser: 150 MHz rtio/jesd clock
2016-11-19 13:16:30 +01:00
02adae7397
drtio: fix link shutdown
2016-11-19 11:01:33 +08:00
abd1b2a94e
drtio: wait longer for remote (bruteforce clock aligner can be slow)
2016-11-19 11:01:09 +08:00
381e58434f
drtio: handle link restarts at transceiver level
2016-11-19 10:46:56 +08:00
0ee47e77ae
phaser: fix widths
2016-11-18 17:24:11 +01:00
bcde26f990
Revert "phaser: cap phy data width to 64 temporarily"
...
This reverts commit 342b9e977e
2016-11-18 17:08:44 +01:00
641f07119f
runtime: support rtio data wider than 64 bit
2016-11-18 17:08:33 +01:00
ba94ed8f4b
drtio: check for absence of disparity errors before claiming RX ready
2016-11-19 00:05:59 +08:00
342b9e977e
phaser: cap phy data width to 64 temporarily
2016-11-18 15:46:59 +01:00
7664b226f2
phaser/conda: bump jesd204b
2016-11-18 15:34:03 +01:00
14ddcd2e30
Revert "dsp/Delay: reset_less"
...
for now
This reverts commit 98193d6fa1
2016-11-18 15:25:42 +01:00
d678bb3fb6
phaser: update sawg tests
2016-11-18 15:23:56 +01:00
whitequark
2015fe9de0
doc: update installing_from_source for LLVM 3.9 transitionl
2016-11-18 10:35:36 +00:00
4d07974a34
drtio: reset link from CPU
2016-11-18 17:45:33 +08:00
f040e27041
drtio: add timeout on FIFO get space request
2016-11-18 17:44:48 +08:00
whitequark
c7844d5223
runtime: use proper format for git commit.
...
Fixes #620 .
2016-11-17 15:20:21 +00:00
bb047aabe9
drtio: simpler link layer
2016-11-17 22:32:39 +08:00
51f23feeac
dsp: implement sawg features
2016-11-17 03:20:37 +01:00
98193d6fa1
dsp/Delay: reset_less
2016-11-17 02:36:29 +01:00
424a1f8f4e
dsp: move test tools
2016-11-16 13:39:19 +01:00
09363e1da8
drtio: aux controller unittest
2016-11-16 19:45:28 +08:00
140bb0ecee
drtio: aux controller fixes
2016-11-16 19:44:03 +08:00
7fa9a4efc3
drtio: aux controller unittest WIP
2016-11-15 12:02:53 +08:00
6c9965b444
drtio: aux controller fixes
2016-11-15 12:02:41 +08:00
e1394db861
drtio: aux controller minor fixes
2016-11-14 17:26:30 +08:00
84bd962ed5
drtio: integrate aux controller
2016-11-14 17:20:47 +08:00
a4d92716da
drtio: fix aux receiver, add aux transmitter
2016-11-14 17:18:54 +08:00
b9ce2bb1f0
Merge branch 'phaser' into phaser2
...
* phaser: (127 commits)
phaser: use misoc cordic
phaser: fix DDS dummy cfg
runtime: disable the Nagle algorithm entirely.
runtime: buffer RPC send packets.
runtime: don't print debug messages to the UART.
runtime: print microsecond timestamps in debug messages.
artiq_devtool: abort if build failed.
conda: bump llvmlite-artiq dep.
conda: bump llvmlite-artiq dep.
llvm_ir_generator: use !{→unconditionally.}invariant.load metadata.
artiq_devtool: more robust port forwarding.
setup: remove paramiko dependency (optional and developer-only)
artiq_devtool: implement.
artiq_compile: actually disable attribute writeback.
conda: use pythonparser 1.0.
conda: tighten pythonparser dependency (fixes #600 ).
doc: clarify kernel_invariant doc (fixes #609 ).
compiler: Emit all-kernel_invariant objects as LLVM constants
conda: update for LLVM 3.9.
add has_dds, use config flags
...
2016-11-13 17:30:37 +01:00
70a70320bd
phaser: use misoc cordic
2016-11-13 17:29:38 +01:00
