3 Commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	99d530e498	targets/ARTIQMiniSoC: remove 2 TTL channels to make room in FPGA	2014-12-01 17:31:35 +08:00
Sebastien Bourdeauducq	1f6441948d	more TTL channels and larger input FIFOs on Papilio Pro	2014-11-30 15:50:57 +08:00
Sebastien Bourdeauducq	8d59f843fb	doc/manual: add FPGA board info and TTL line assignments	2014-11-21 16:39:22 -08:00