Commit Graph

7417 Commits

Author SHA1 Message Date
62d7c89c48 sayma_amc: use high-resolution TTL on SMAs (#792) 2019-01-03 20:50:38 +08:00
0972d61e81 ttl_serdes_ultrascale: use GTH clock domains 2019-01-03 20:50:04 +08:00
f007895fad drtio/gth_ultrascale: fix rtiox clock domain 2019-01-03 20:49:38 +08:00
10ebf63c47 jesd204_tools: get the Vivado timing analyzer to behave 2019-01-03 20:22:35 +08:00
d6a3172a3e update copyright year 2019-01-03 20:21:34 +08:00
4af8fd6a0d ttl_serdes_ultrascale: fix Input 2019-01-03 20:14:54 +08:00
175f8b8ccc drtio/gth_ultrascale: generate multiplied RTIO clock from BUFG_GT (#792) 2019-01-03 20:14:18 +08:00
77126ce5b3 kasli: use hwrev 1.1 by default for DRTIO examples 2019-01-02 23:04:20 +08:00
ab9ca0ee0a kasli: use 150MHz for DRTIO by default (Sayma compatibility) 2019-01-02 23:03:57 +08:00
cc58318500 siphaser: autocalibrate skew using RX synchronizer
* removes the hardcoded, (poorly) manually determined skew value
* does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)
2019-01-02 22:29:27 +08:00
f5cda3689e sayma_amc: enable DRTIO on master SATA connector for MasterDAC variant 2019-01-02 16:46:16 +08:00
e85df13127 nix: update docs 2019-01-02 16:34:29 +08:00
ec52a1003d nix: add jesd204b 2019-01-02 16:34:11 +08:00
d42d607547 nix: add microscope 2019-01-02 16:13:08 +08:00
7a6bdcb041 nix: fix m-labs URLs 2019-01-02 16:04:25 +08:00
48793b7ecf nix: reorganize .nix files 2019-01-01 23:39:38 +08:00
e2799803cb nix: do not install development packages in user environment 2019-01-01 23:35:55 +08:00
1e7ba3227f nix: add development environment 2019-01-01 22:26:32 +08:00
421ad9c916 nix: bump llvmlite 2018-12-22 14:01:52 +08:00
e80d80f133 manual: move to correct directory for building rust crates. Closes #1222 2018-12-21 10:37:08 +08:00
Drew
d60b95f481 tdr.py: typo (#1220) 2018-12-18 18:47:09 +00:00
a7d4d3bda9 ad9910: CONT_RECIRCULATE -> CONT_RAMPUP 2018-12-17 13:25:00 +00:00
35bdf26f01 Merge branch 'ad9910-ram' 2018-12-17 21:16:44 +08:00
David Nadlinger
e608d6ffd3 coredevice, firmware: Add rtio_input_timestamped_data
Integration tests to follow as part of an RTIO counter phy that
makes use of this.
2018-12-15 00:35:04 +00:00
David Nadlinger
8e30c4574b firmware: Treat timestamps consistently as signed [nfc]
This matches other functions and the ARTIQ Python side, but
isn't actually an ABI change.
2018-12-15 00:02:18 +00:00
38ce7ab8ff sync_struct: handle TimeoutError as subscriber disconnection. Closes #1215 2018-12-13 06:58:54 +08:00
c09ab8502c nix: cleanup 2018-12-13 06:57:10 +08:00
Joachim Schiele
73941d4661 nix: add rustc, migen and misoc
This allows firmware compilation.
2018-12-12 22:24:55 +00:00
79eadb9465 ad9910: add RAM mode methods
* also refactor the CFR1 access into a method

c.f. #1154

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 14:54:16 +00:00
6df4ae934f eem: name the servo submodule
This allows the migen namer to derive names for the ADC return clock
domain in the case of multiple SUServos

close #1201

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 11:36:40 +01:00
efd400b02c ad9910: style [nfc]
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-11 11:36:25 +01:00
David Nadlinger
d4c393b2a8 firmware/ksupport: Update cfg(not(has_rtio)) stub signatures
This fixes up 8caea0e6d3,
but it is unclear whether anyone even uses a `not(has_rtio)`
configuration at this point.
2018-12-11 01:22:48 +00:00
d90eb3ae88 ad9910: add read64()
Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-07 21:27:00 +00:00
baf88050fd urukul: expand attenuator HITL unittests
* read back with cleared backing state
* individual channel settings
* check backing state

Signed-off-by: Robert Jördens <rj@quartiq.de>
2018-12-07 21:06:12 +00:00
Kaifeng
cc143d5fec kasli_tester: add support for windows platform. (#1204) 2018-12-05 14:06:45 +01:00
6aa341bc44 test_loopback_gate_timing: fix lat_offset 2018-12-02 20:52:32 +08:00
421834fa3e compiler: document Target.little_endian 2018-12-02 19:07:18 +08:00
981a77834a compiler: use default triple to determine data_layout for JIT 2018-12-02 18:52:13 +08:00
d931967e5c fix previous commits 2018-12-02 18:32:03 +08:00
dd03fdfd1a typo 2018-12-02 18:26:54 +08:00
8940009e1a compiler: pass data_layout string to llvm.create_target_data before determining endianness 2018-12-02 18:26:19 +08:00
2e66788c6c compiler: support little endian target when storing now 2018-12-02 17:40:34 +08:00
ad39c76a56 conda: fix llvmlite dependency 2018-12-02 06:40:00 +08:00
7e14f3ca4e compiler,gateware: atomic now stores 2018-12-02 05:06:46 +08:00
fd00021a52 ctlmgr: do not raise exceptions in Controllers.__setitem__. Closes #1198 2018-12-01 18:09:58 +08:00
7f55376c75 test_loopback_gate_timing: print input timing for debugging 2018-12-01 18:09:53 +08:00
dce4f036db grabber: work around windows numpy int peculiarity (same as a81c12de9) 2018-11-30 18:41:14 +08:00
156afb48ee language: fix syscall arg handling 2018-11-30 17:59:24 +08:00
Paweł K
57caa7b149 artiq_flash: add command to erase flash memory (#1197) 2018-11-28 12:33:32 +02:00
3fd95b86c2 typo 2018-11-26 17:54:55 +08:00