b452789f03
Merge branch 'master' into nac3
2022-01-19 21:07:10 +08:00
4e3e0d129c
firmware: fix compilation warning
2022-01-11 09:31:26 +08:00
12ee326fb4
firmware: fixed personality function
2022-01-11 09:30:19 +08:00
Steve Fan
4a6bea479a
Host report for async error upon kernel termination ( #1791 )
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Closes #1644
2021-12-04 13:33:24 +08:00
f281112779
satman: add 100mhz si5324 settings
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siphaser: add calculated vco for 100mhz comment
2021-12-03 17:19:11 +08:00
9423428bb0
drtio: fix crc32 offset address
2021-11-24 12:00:56 +08:00
34789767f0
firmware: fix compilation warning
2021-11-22 18:23:28 +08:00
db3e5e83e6
bump misoc
2021-11-08 16:59:08 +08:00
531670d6c5
dyld: check ABI
2021-11-08 16:59:08 +08:00
03b803e764
firmware: adjust csr separation
2021-11-08 16:59:08 +08:00
b3e315e24a
rust: find json file using CARGO_TRIPLE
2021-11-08 16:59:08 +08:00
0898e101e2
board_misoc: reuse riscv dir for comm & kernel
2021-11-08 16:59:08 +08:00
69cddc6b86
rtio_clocking: add warnings for unsupported rtio_clock settings ( #1773 )
2021-10-28 16:34:22 +08:00
9b1d7e297d
runtime: clock input specification improvements
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closes #1735
2021-10-28 16:21:51 +08:00
d5fa3d131a
cargo.lock: update libc version for libfringe
2021-10-16 17:42:24 +08:00
6d3164a912
riscv: print mtval on panic
2021-10-16 17:42:24 +08:00
46326716fd
runtime: bump libfringe, impl ecall abi
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See libfringe PR: M-Labs/libfringe#1
2021-10-16 17:42:24 +08:00
0a59c889de
satman/kern: init locked PMP on startup
2021-10-16 17:42:24 +08:00
27a7a96626
runtime: setup pmp + transfer to user
2021-10-16 17:42:24 +08:00
a0bf11b465
riscv: impl pmp
2021-10-16 17:42:24 +08:00
790a20edf6
linker: generate stack guard + symbol
2021-10-16 17:42:24 +08:00
35d21c98d3
Revert "runtime: expose rint from libm"
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Consistency with NAR3/Zynq where rint is not available.
This reverts commit f5100702f6
2021-10-11 08:12:04 +08:00
f5100702f6
runtime: expose rint from libm
2021-10-10 20:40:17 +08:00
59065c4663
alloc_list: support alloc w/ large align
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Signed-off-by: Oi Chee Cheung <dc@m-labs.hk>
2021-10-07 12:38:03 +08:00
2d79d824f9
firmware: remove minor or1k leftovers
2021-09-12 20:03:37 +08:00
a573dcf3f9
board_misoc/build: use rv32 as target arg
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The original rv64 argument was only to match the misoc counterpart.
2021-09-10 14:11:23 +08:00
448974fe11
runtime/main: cleanup
2021-09-10 13:59:53 +08:00
b091d8cb66
kernel: flush cache before mod_init
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This could be necessary as redirecting instructions from D$ directly to I$ as it seems.
Related: https://github.com/SpinalHDL/VexRiscv/issues/137
2021-09-10 13:25:12 +08:00
b8ed5a0d91
alloc: fix alignment for riscv32 arch
2021-09-10 13:25:12 +08:00
2213e7ffac
ksupp/rtio/exception: fix timestamp
2021-09-10 13:25:12 +08:00
09ffd9de1e
dma: fix timestamp fetch
2021-09-10 13:25:12 +08:00
c6ba0f3cf4
ksupport: fix dma cslice (ffi)
2021-09-10 13:25:12 +08:00
c812a837ab
runtime: enlarge stack size
2021-09-10 13:25:12 +08:00
a596db404d
satman: fix cargo xbuild sysroot
2021-09-10 13:25:12 +08:00
4fab267593
cargo: std dependency hack
2021-09-10 13:25:12 +08:00
dcbd9f905c
cargo: use cargo xbuild
2021-09-10 13:25:12 +08:00
9f6b3f6014
firmware: clarify target triple
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The lack of compressed instruction support can be inferred from the target triple, literally.
2021-09-10 13:25:12 +08:00
6db7280b09
flake: board package WIP
2021-09-10 13:25:12 +08:00
d8ac429059
dyld: streamline lib.rs
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Only riscv32 is supported anyway, no need to have excessive architecture check.
2021-09-10 13:25:12 +08:00
798774192d
slave_fpga/bootloader: read in little endian
2021-09-10 13:25:12 +08:00
eecd825d23
firmware: suppress warning
2021-09-10 13:25:12 +08:00
1da0554a49
pcr: purge
2021-09-10 13:25:12 +08:00
70507e1b72
Cargo.lock: update
2021-09-10 13:25:12 +08:00
c113cd6bf5
libfringe: bump
2021-09-10 13:25:12 +08:00
61b0170a12
firmware: purge or1k
2021-09-10 13:25:12 +08:00
af263ffe1f
ksupport: fix rpc, cache signature (FFI)
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The reason of the borrow stuff is explained in M-Labs/artiq-zynq#76 (artiq-zyna repo).
As for `cache_get()`, compiler will perform stack allocation to pre-allocate the returned structure, and pass to cache_get alongside the `key`.
However, ksupport fails to recognize the passed memory, so it will always assume the passed memory as the key.
2021-09-10 13:25:12 +08:00
8fa47b8119
rpc: enforce alignment
2021-09-10 13:25:12 +08:00
de0f2d4a28
firmware: adopt endianness protocol in artiq-zynq
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Related:
artiq-zynq: M-Labs/artiq-zynq#126
artiq: #1588
2021-09-10 13:25:12 +08:00
9afe63c08a
ksupport: fix proto_artiq dependency
2021-09-10 13:25:12 +08:00
29a2f106d1
ksupport: replace asm with llvm_asm
2021-09-10 13:25:12 +08:00
