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runtime/dds: fix AD9914 register initialization values 

Thanks Raghavendra Srinivas for the help. Closes #114.
This commit is contained in:
Sebastien Bourdeauducq 2015-08-27 10:47:44 +08:00
parent 1991b3c910
commit f07c7e9c6f
3 changed files with 6 additions and 1 deletions
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4
soc/runtime/dds.c
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@ -18,7 +18,7 @@
/* DAC calibration takes max. 135us as per datasheet. Take a good margin. */ /* DAC calibration takes max. 135us as per datasheet. Take a good margin. */
#define DURATION_DAC_CAL (30000 << RTIO_FINE_TS_WIDTH) #define DURATION_DAC_CAL (30000 << RTIO_FINE_TS_WIDTH)
/* not counting final FUD */ /* not counting final FUD */
#define DURATION_INIT (8*DURATION_WRITE + DURATION_DAC_CAL) #define DURATION_INIT (10*DURATION_WRITE + DURATION_DAC_CAL)
#define DURATION_PROGRAM (5*DURATION_WRITE) /* not counting FUD */ #define DURATION_PROGRAM (5*DURATION_WRITE) /* not counting FUD */
#else #else
@ -79,6 +79,8 @@ void dds_init(long long int timestamp, int channel)
#ifdef DDS_AD9914 #ifdef DDS_AD9914
DDS_WRITE(DDS_CFR1H, 0x0000); /* Enable cosine output */ DDS_WRITE(DDS_CFR1H, 0x0000); /* Enable cosine output */
DDS_WRITE(DDS_CFR2L, 0x8900); /* Enable matched latency */ DDS_WRITE(DDS_CFR2L, 0x8900); /* Enable matched latency */
DDS_WRITE(DDS_CFR2H, 0x0080); /* Enable profile mode */
DDS_WRITE(DDS_ASF, 0x0fff); /* Set amplitude to maximum */
DDS_WRITE(DDS_CFR4H, 0x0105); /* Enable DAC calibration */ DDS_WRITE(DDS_CFR4H, 0x0105); /* Enable DAC calibration */
DDS_WRITE(DDS_FUD, 0); DDS_WRITE(DDS_FUD, 0);
now += DURATION_DAC_CAL; now += DURATION_DAC_CAL;

1
soc/runtime/dds.h
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@ -35,6 +35,7 @@
#define DDS_FTWL 0x2d #define DDS_FTWL 0x2d
#define DDS_FTWH 0x2f #define DDS_FTWH 0x2f
#define DDS_POW 0x31 #define DDS_POW 0x31
#define DDS_ASF 0x33
#define DDS_FUD 0x80 #define DDS_FUD 0x80
#define DDS_GPIO 0x81 #define DDS_GPIO 0x81
#endif #endif

2
soc/runtime/test_mode.c
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@ -239,6 +239,8 @@ static void ddsinit(void)
brg_ddsreset(); brg_ddsreset();
brg_ddswrite(DDS_CFR1H, 0x0000); /* Enable cosine output */ brg_ddswrite(DDS_CFR1H, 0x0000); /* Enable cosine output */
brg_ddswrite(DDS_CFR2L, 0x8900); /* Enable matched latency */ brg_ddswrite(DDS_CFR2L, 0x8900); /* Enable matched latency */
brg_ddswrite(DDS_CFR2H, 0x0080); /* Enable profile mode */
brg_ddswrite(DDS_ASF, 0x0fff); /* Set amplitude to maximum */
brg_ddswrite(DDS_CFR4H, 0x0105); /* Enable DAC calibration */ brg_ddswrite(DDS_CFR4H, 0x0105); /* Enable DAC calibration */
brg_ddswrite(DDS_FUD, 0); brg_ddswrite(DDS_FUD, 0);
t = clock_get_ms(); t = clock_get_ms();