coredevice/TTLClockGen: fix attribute init

2015-08-27 09:48:11 +08:00 · 2015-08-27 09:48:11 +08:00 · 1991b3c910
parent 4cb0d4589e
commit 1991b3c910
1 changed files with 0 additions and 1 deletions
--- a/artiq/coredevice/ttl.py
+++ b/artiq/coredevice/ttl.py
@ -220,7 +220,6 @@ class TTLClockGen:
        self.core = dmgr.get("core")
        self.channel = channel

-    def build(self):
        # in RTIO cycles
        self.previous_timestamp = int64(0)
        self.acc_width = 24