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kc705: switch backplane spi to spi2

This commit is contained in:
Robert Jördens 2018-02-23 17:26:51 +01:00
parent 6fbe0d8ed8
commit ec5b81da55
1 changed files with 3 additions and 3 deletions
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6
artiq/gateware/targets/kc705.py
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@ -17,7 +17,7 @@ from misoc.integration.builder import builder_args, builder_argdict
from artiq.gateware.amp import AMPSoC from artiq.gateware.amp import AMPSoC
from artiq.gateware import rtio, nist_clock, nist_qc2 from artiq.gateware import rtio, nist_clock, nist_qc2
from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series, from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
dds, spi, spi2, ad5360_monitor) dds, spi2, ad5360_monitor)
from artiq.build_soc import build_artiq_soc from artiq.build_soc import build_artiq_soc
from artiq import __version__ as artiq_version from artiq import __version__ as artiq_version
@ -325,7 +325,7 @@ class NIST_CLOCK(_StandaloneBase):
phy, ififo_depth=4)) phy, ififo_depth=4))
for i in range(3): for i in range(3):
phy = spi.SPIMaster(self.platform.request("spi", i)) phy = spi2.SPIMaster(self.platform.request("spi", i))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy( rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=128)) phy, ififo_depth=128))
@ -429,7 +429,7 @@ class NIST_QC2(_StandaloneBase):
phy, ififo_depth=4)) phy, ififo_depth=4))
for i in range(4): for i in range(4):
phy = spi.SPIMaster(self.platform.request("spi", i)) phy = spi2.SPIMaster(self.platform.request("spi", i))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy( rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=128)) phy, ififo_depth=128))