forked from M-Labs/artiq
kc705: switch backplane spi to spi2
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@ -17,7 +17,7 @@ from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
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dds, spi, spi2, ad5360_monitor)
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dds, spi2, ad5360_monitor)
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from artiq.build_soc import build_artiq_soc
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from artiq import __version__ as artiq_version
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@ -325,7 +325,7 @@ class NIST_CLOCK(_StandaloneBase):
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phy, ififo_depth=4))
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for i in range(3):
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phy = spi.SPIMaster(self.platform.request("spi", i))
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phy = spi2.SPIMaster(self.platform.request("spi", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=128))
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@ -429,7 +429,7 @@ class NIST_QC2(_StandaloneBase):
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phy, ififo_depth=4))
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for i in range(4):
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phy = spi.SPIMaster(self.platform.request("spi", i))
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phy = spi2.SPIMaster(self.platform.request("spi", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ififo_depth=128))
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