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drtio: initialize AD9516 clock chip

This commit is contained in:
Sebastien Bourdeauducq 2017-01-30 11:06:45 +08:00
parent 54295b1699
commit d8e9949266
3 changed files with 20 additions and 0 deletions
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3
artiq/firmware/satman/lib.rs
View File

@ -14,6 +14,9 @@ fn startup() {
info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
info!("gateware version {}", board::ident(&mut [0; 64]));
#[cfg(has_ad9516)]
board::ad9516::init().expect("cannot initialize ad9516");
loop {}
}

9
artiq/gateware/targets/kc705_drtio_master.py
View File

@ -5,6 +5,7 @@ import argparse
from migen import *
from migen.build.generic_platform import *
from misoc.cores import spi as spi_csr
from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
from misoc.integration.soc_core import mem_decoder
from misoc.integration.builder import builder_args, builder_argdict
@ -59,6 +60,14 @@ class Master(MiniSoC, AMPSoC):
tx_pads=tx_pads,
rx_pads=rx_pads,
sys_clk_freq=self.clk_freq)
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.config["CONVERTER_SPI_DAC_CS"] = 0
self.config["CONVERTER_SPI_CLK_CS"] = 1
self.config["HAS_AD9516"] = None
else:
raise ValueError
self.submodules.drtio = DRTIOMaster(self.transceiver)

8
artiq/gateware/targets/kc705_drtio_satellite.py
View File

@ -175,6 +175,14 @@ class Satellite(BaseSoC):
tx_pads=tx_pads,
rx_pads=rx_pads,
sys_clk_freq=self.clk_freq)
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.config["CONVERTER_SPI_DAC_CS"] = 0
self.config["CONVERTER_SPI_CLK_CS"] = 1
self.config["HAS_AD9516"] = None
else:
raise ValueError
self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(