forked from M-Labs/artiq
123 lines
4.7 KiB
Python
Executable File
123 lines
4.7 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.build.generic_platform import *
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from misoc.cores import spi as spi_csr
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from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.soc_core import mem_decoder
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
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from artiq.gateware.amp import AMPSoC, build_artiq_soc
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio import DRTIOMaster
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from artiq import __version__ as artiq_version
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class Master(MiniSoC, AMPSoC):
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mem_map = {
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"drtio_aux": 0x50000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, cfg, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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**kwargs)
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AMPSoC.__init__(self)
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platform = self.platform
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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tx_pads = platform.request("sfp_tx")
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rx_pads = platform.request("sfp_rx")
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if cfg == "simple_gbe":
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# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
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# simple TTLs
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self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
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clock_pads=platform.request("sgmii_clock"),
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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sys_clk_freq=self.clk_freq,
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clock_div2=True)
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elif cfg == "sawg_3g":
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# 3Gb link, 150MHz RTIO clock
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# with SAWG on local RTIO and AD9154-FMC-EBZ
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platform.add_extension(ad9154_fmc_ebz)
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self.submodules.transceiver = gtx_7series.GTX_3G(
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clock_pads=platform.request("ad9154_refclk"),
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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sys_clk_freq=self.clk_freq)
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ad9154_spi = platform.request("ad9154_spi")
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self.comb += ad9154_spi.en.eq(1)
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self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
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self.csr_devices.append("converter_spi")
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self.config["CONVERTER_SPI_DAC_CS"] = 0
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self.config["CONVERTER_SPI_CLK_CS"] = 1
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self.config["HAS_AD9516"] = None
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else:
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raise ValueError
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self.submodules.drtio = DRTIOMaster(self.transceiver)
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self.csr_devices.append("drtio")
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self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]),
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self.drtio.aux_controller.bus)
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self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
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platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
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platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.transceiver.txoutclk, self.transceiver.rxoutclk)
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rtio_channels = []
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for i in range(8):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for sma in "user_sma_gpio_p", "user_sma_gpio_n":
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phy = ttl_simple.Inout(platform.request(sma))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_core = rtio.Core(rtio_channels, 3)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.drtio.cri, self.rtio_core.cri])
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder / KC705 DRTIO master")
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builder_args(parser)
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soc_kc705_args(parser)
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parser.add_argument("-c", "--config", default="simple_gbe",
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help="configuration: simple_gbe/sawg_3g "
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"(default: %(default)s)")
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args = parser.parse_args()
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soc = Master(args.config, **soc_kc705_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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if __name__ == "__main__":
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main()
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