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gateware/targets: add RTIO log channels

This commit is contained in:
Sebastien Bourdeauducq 2015-12-26 22:44:01 +08:00
parent 080752092c
commit ba6c527819
2 changed files with 11 additions and 0 deletions
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8
artiq/gateware/targets/kc705.py
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@ -185,6 +185,10 @@ class NIST_QC1(_NIST_QCx):
rtio_channels.append(rtio.Channel.from_phy(phy, rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=512, ofifo_depth=512,
ififo_depth=4)) ififo_depth=4))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels) self.add_rtio(rtio_channels)
@ -230,6 +234,10 @@ class NIST_QC2(_NIST_QCx):
rtio_channels.append(rtio.Channel.from_phy(phy, rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=512, ofifo_depth=512,
ififo_depth=4)) ififo_depth=4))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels) self.add_rtio(rtio_channels)

3
artiq/gateware/targets/pipistrello.py
View File

@ -190,6 +190,9 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
ofifo_depth=512, ofifo_depth=512,
ififo_depth=4)) ififo_depth=4))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
# RTIO core # RTIO core
self.submodules.rtio = rtio.RTIO(rtio_channels) self.submodules.rtio = rtio.RTIO(rtio_channels)
self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width