From ba6c5278190b9bc04f7cb81bf571d1c6c6ce0740 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 26 Dec 2015 22:44:01 +0800 Subject: [PATCH] gateware/targets: add RTIO log channels --- artiq/gateware/targets/kc705.py | 8 ++++++++ artiq/gateware/targets/pipistrello.py | 3 +++ 2 files changed, 11 insertions(+) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 0cfad4faf..a61bda8c7 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -185,6 +185,10 @@ class NIST_QC1(_NIST_QCx): rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=512, ififo_depth=4)) + + self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) + rtio_channels.append(rtio.LogChannel()) + self.add_rtio(rtio_channels) @@ -230,6 +234,10 @@ class NIST_QC2(_NIST_QCx): rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=512, ififo_depth=4)) + + self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) + rtio_channels.append(rtio.LogChannel()) + self.add_rtio(rtio_channels) diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py index a417209f4..11eef2072 100755 --- a/artiq/gateware/targets/pipistrello.py +++ b/artiq/gateware/targets/pipistrello.py @@ -190,6 +190,9 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd ofifo_depth=512, ififo_depth=4)) + self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) + rtio_channels.append(rtio.LogChannel()) + # RTIO core self.submodules.rtio = rtio.RTIO(rtio_channels) self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width