forked from M-Labs/artiq
kc705: add multichannel support on satellite
* Two DRTIO channels (i.e. satellite and repeater) are enabled by default. * User can choose either the SFP or SMA as the satellite channel (by passing `--drtio-sat sfp` or --drtio-sat sma` to the argparser), and the unchosen would become the repeater channel.
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@ -31,13 +31,15 @@ class Satellite(BaseSoC):
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, gateware_identifier_str=None, **kwargs):
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def __init__(self, gateware_identifier_str=None, drtio_sat="sfp", **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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**kwargs)
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assert drtio_sat in ["sfp", "sma"]
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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@ -50,8 +52,15 @@ class Satellite(BaseSoC):
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platform = self.platform
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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tx_pads = [platform.request("sfp_tx")]
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rx_pads = [platform.request("sfp_rx")]
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tx_pads = [
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platform.request("sfp_tx"), platform.request("user_sma_mgt_tx")
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]
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rx_pads = [
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platform.request("sfp_rx"), platform.request("user_sma_mgt_rx")
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]
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if drtio_sat == "sma":
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tx_pads = tx_pads[::-1]
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rx_pads = rx_pads[::-1]
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# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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@ -62,24 +71,49 @@ class Satellite(BaseSoC):
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
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self.submodules.drtiosat = cdr(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer))
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self.csr_devices.append("drtiosat")
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtiorep_csr_group = []
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self.drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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self.submodules.drtioaux0 = cdr(DRTIOAuxController(
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self.drtiosat.link_layer))
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self.csr_devices.append("drtioaux0")
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self.add_wb_slave(self.mem_map["drtioaux"], 0x800,
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self.drtioaux0.bus)
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self.add_memory_region("drtioaux0_mem", self.mem_map["drtioaux"] | self.shadow_base, 0x800)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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# Satellite
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if i == 0:
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
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core = cdr(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer))
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self.submodules.drtiosat = core
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self.csr_devices.append("drtiosat")
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# Repeaters
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else:
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corerep_name = "drtiorep" + str(i-1)
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drtiorep_csr_group.append(corerep_name)
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core = cdr(DRTIORepeater(
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self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, corerep_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(corerep_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtiosat"])
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self.add_csr_group("drtioaux", ["drtioaux0"])
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self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
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# Si5324 Phaser
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@ -135,7 +169,13 @@ class Satellite(BaseSoC):
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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self.comb += self.drtiosat.cri.connect(self.local_io.cri)
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.drtiosat.cri],
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[self.local_io.cri] + self.drtio_cri,
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mode="sync", enable_routing=True)
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self.csr_devices.append("cri_con")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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def main():
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@ -144,9 +184,15 @@ def main():
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builder_args(parser)
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soc_kc705_args(parser)
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parser.set_defaults(output_dir="artiq_kc705/satellite")
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parser.add_argument("--drtio-sat", default="sfp",
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help="use the SFP or the SMA connectors (RX: J17, J18, TX: J19, J20) "
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"as DRTIO satellite channel (choices: sfp, sma; default: sfp)")
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args = parser.parse_args()
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soc = Satellite(**soc_kc705_argdict(args))
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argdict = dict()
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argdict["drtio_sat"] = args.drtio_sat
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soc = Satellite(**soc_kc705_argdict(args), **argdict)
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build_artiq_soc(soc, builder_argdict(args))
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