drtio/iot: FIFO level

2016-10-19 18:04:03 +08:00 · 2016-10-19 18:04:03 +08:00 · 9790c5d9ed
commit 9790c5d9ed
parent 71480c4d15
1 changed files with 6 additions and 0 deletions
--- a/artiq/gateware/drtio/iot.py
+++ b/artiq/gateware/drtio/iot.py
@ -39,6 +39,12 @@ class IOT(Module):
                fifo_out.raw_bits().eq(fifo.dout)
            ]

+            # FIFO level
+            self.sync += \
+                If(rt_packets.fifo_level_update &
+                   (rt_packets.fifo_level_channel == n),
+                    rt_packets.fifo_level.eq(fifo.level))
+
            # FIFO write
            self.comb += fifo.we.eq(rt_packets.write_stb)
            self.sync += \