From 9790c5d9edd84ca1a767ebe20f521ba9ee7a7522 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 19 Oct 2016 18:04:03 +0800
Subject: [PATCH] drtio/iot: FIFO level

---
 artiq/gateware/drtio/iot.py | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/artiq/gateware/drtio/iot.py b/artiq/gateware/drtio/iot.py
index f8e07c299..c05e6b1a7 100644
--- a/artiq/gateware/drtio/iot.py
+++ b/artiq/gateware/drtio/iot.py
@@ -39,6 +39,12 @@ class IOT(Module):
                 fifo_out.raw_bits().eq(fifo.dout)
             ]
 
+            # FIFO level
+            self.sync += \
+                If(rt_packets.fifo_level_update &
+                   (rt_packets.fifo_level_channel == n),
+                    rt_packets.fifo_level.eq(fifo.level))
+
             # FIFO write
             self.comb += fifo.we.eq(rt_packets.write_stb)
             self.sync += \