drtio: fix typo

2016-11-09 22:15:42 +08:00 · 2016-11-09 22:15:42 +08:00 · 8a48d6d66e
parent 863934c4fa
commit 8a48d6d66e
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/drtio/transceiver/gtx_7series.py
+++ b/artiq/gateware/drtio/transceiver/gtx_7series.py
@ -228,7 +228,7 @@ class RXSynchronizer(Module, AutoCSR):

                p_CLKFBOUT_MULT_F=mmcm_mult,
                p_CLKOUT0_DIVIDE_F=mmcm_mult,
-                p_CLKOUT0_PHASE=intial_phase,
+                p_CLKOUT0_PHASE=initial_phase,
                p_DIVCLK_DIVIDE=1,

                # According to Xilinx, there is no guarantee of input/output