From 8a48d6d66e6b308d9ae26c1a80f8f9aca2495ca9 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 9 Nov 2016 22:15:42 +0800 Subject: [PATCH] drtio: fix typo --- artiq/gateware/drtio/transceiver/gtx_7series.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/drtio/transceiver/gtx_7series.py b/artiq/gateware/drtio/transceiver/gtx_7series.py index 8653dbe33..00166e11f 100644 --- a/artiq/gateware/drtio/transceiver/gtx_7series.py +++ b/artiq/gateware/drtio/transceiver/gtx_7series.py @@ -228,7 +228,7 @@ class RXSynchronizer(Module, AutoCSR): p_CLKFBOUT_MULT_F=mmcm_mult, p_CLKOUT0_DIVIDE_F=mmcm_mult, - p_CLKOUT0_PHASE=intial_phase, + p_CLKOUT0_PHASE=initial_phase, p_DIVCLK_DIVIDE=1, # According to Xilinx, there is no guarantee of input/output