forked from M-Labs/artiq
fastino: use fastlink
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@ -4,132 +4,7 @@ from migen.genlib.io import DifferentialOutput, DifferentialInput, DDROutput
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
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from artiq.gateware.rtio import rtlink
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class SerDes(Module):
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def transpose(self, i, n):
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# i is n,m c-contiguous
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# o is m,n c-contiguous
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m = len(i)//n
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assert n*m == len(i)
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def __init__(self, pins, pins_n):
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n_bits = 16 # bits per dac data word
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n_channels = 32 # channels per fastino
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n_div = 7 # bits per lane and word
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assert n_div == 7
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n_frame = 14 # word per frame
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n_lanes = len(pins.mosi) # number of data lanes
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n_checksum = 12 # checksum bits
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n_addr = 4 # readback address bits
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n_word = n_lanes*n_div
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n_body = n_word*n_frame - (n_frame//2 + 1) - n_checksum
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# dac data words
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self.dacs = [Signal(n_bits) for i in range(n_channels)]
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# dac update enable
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self.enable = Signal(n_channels)
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# configuration word
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self.cfg = Signal(20)
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# readback data
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self.dat_r = Signal(n_frame//2*(1 << n_addr))
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# data load synchronization event
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self.stb = Signal()
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# # #
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# crc-12 telco
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self.submodules.crc = LiteEthMACCRCEngine(
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data_width=2*n_lanes, width=n_checksum, polynom=0x80f)
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addr = Signal(4)
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body_ = Cat(self.cfg, addr, self.enable, self.dacs)
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assert len(body_) == n_body
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body = Signal(n_body)
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self.comb += body.eq(body_)
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words_ = []
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j = 0
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for i in range(n_frame): # iterate over words
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if i == 0: # data and checksum
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k = n_word - n_checksum
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elif i == 1: # marker
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words_.append(C(1))
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k = n_word - 1
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elif i < n_frame//2 + 2: # marker
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words_.append(C(0))
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k = n_word - 1
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else: # full word
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k = n_word
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# append corresponding frame body bits
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words_.append(body[j:j + k])
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j += k
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words_ = Cat(words_)
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assert len(words_) == n_frame*n_word - n_checksum
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words = Signal(len(words_))
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self.comb += words.eq(words_)
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clk = Signal(n_div, reset=0b1100011)
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clk_stb = Signal()
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i_frame = Signal(max=n_div*n_frame//2) # DDR
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frame_stb = Signal()
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sr = [Signal(n_frame*n_div - n_checksum//n_lanes, reset_less=True)
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for i in range(n_lanes)]
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assert len(Cat(sr)) == len(words)
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# DDR bits for each register
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ddr_data = Cat([sri[-2] for sri in sr], [sri[-1] for sri in sr])
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self.comb += [
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# assert one cycle ahead
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clk_stb.eq(~clk[0] & clk[-1]),
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# double period because of DDR
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frame_stb.eq(i_frame == n_div*n_frame//2 - 1),
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# LiteETHMACCRCEngine takes data LSB first
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self.crc.data[::-1].eq(ddr_data),
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self.stb.eq(frame_stb & clk_stb),
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]
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miso = Signal()
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miso_sr = Signal(n_frame, reset_less=True)
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self.sync.rio_phy += [
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# shift 7 bit clock pattern by two bits each DDR cycle
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clk.eq(Cat(clk[-2:], clk)),
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[sri[2:].eq(sri) for sri in sr],
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self.crc.last.eq(self.crc.next),
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If(clk[:2] == 0, # TODO: tweak MISO sampling
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miso_sr.eq(Cat(miso, miso_sr)),
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),
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If(~frame_stb,
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i_frame.eq(i_frame + 1),
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),
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If(frame_stb & clk_stb,
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i_frame.eq(0),
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self.crc.last.eq(0),
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# transpose, load
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Cat(sr).eq(Cat(words[mm::n_lanes] for mm in range(n_lanes))),
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Array([self.dat_r[i*n_frame//2:(i + 1)*n_frame//2]
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for i in range(1 << len(addr))])[addr].eq(miso_sr),
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addr.eq(addr + 1),
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),
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If(i_frame == n_div*n_frame//2 - 2,
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# inject crc
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ddr_data.eq(self.crc.next),
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),
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]
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clk_ddr = Signal()
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miso0 = Signal()
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self.specials += [
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DDROutput(clk[-1], clk[-2], clk_ddr, ClockSignal("rio_phy")),
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DifferentialOutput(clk_ddr, pins.clk, pins_n.clk),
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DifferentialInput(pins.miso, pins_n.miso, miso0),
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MultiReg(miso0, miso, "rio_phy"),
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]
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for sri, ddr, mp, mn in zip(
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sr, Signal(n_lanes), pins.mosi, pins_n.mosi):
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self.specials += [
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DDROutput(sri[-1], sri[-2], ddr, ClockSignal("rio_phy")),
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DifferentialOutput(ddr, mp, mn),
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]
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from .fastlink import SerDes, SerInterface
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class Fastino(Module):
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@ -139,9 +14,31 @@ class Fastino(Module):
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rtlink.OInterface(data_width=max(16*width, 32),
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address_width=8,
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enable_replace=False),
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rtlink.IInterface(data_width=32))
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rtlink.IInterface(data_width=14))
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self.submodules.serializer = SerDes(pins, pins_n)
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self.submodules.serializer = SerDes(
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n_data=8, t_clk=7, d_clk=0b1100011,
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n_frame=14, n_crc=12, poly=0x80f)
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self.submodules.intf = SerInterface(pins, pins_n)
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self.comb += [
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Cat(self.intf.data[:-1]).eq(Cat(self.serializer.data[:-1])),
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self.serializer.data[-1].eq(self.intf.data[-1]),
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]
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# dac data words
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dacs = [Signal(16) for i in range(32)]
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header = Record([
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("cfg", 4),
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("leds", 8),
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("reserved", 8),
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("addr", 4),
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("enable", len(dacs)),
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])
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body = Cat(header.raw_bits(), dacs)
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assert len(body) == len(self.serializer.payload)
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self.comb += self.serializer.payload.eq(body)
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# # #
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# Support staging DAC data (in `dacs`) by writing to the
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# DAC RTIO addresses, if a channel is not "held" by its
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@ -164,37 +61,36 @@ class Fastino(Module):
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# LSBs of the RTIO address for a DAC channel write must be zero and the
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# address space is sparse.
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hold = Signal.like(self.serializer.enable)
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hold = Signal.like(header.enable)
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# TODO: stb, timestamp
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read_regs = Array([
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self.serializer.dat_r[i*7:(i + 1)*7]
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for i in range(1 << 4)
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])
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read_regs = Array([Signal.like(self.serializer.readback)
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for _ in range(1 << len(header.addr))])
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cases = {
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# update
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0x20: self.serializer.enable.eq(self.serializer.enable | self.rtlink.o.data),
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0x20: header.enable.eq(header.enable | self.rtlink.o.data),
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# hold
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0x21: hold.eq(self.rtlink.o.data),
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# cfg
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0x22: self.serializer.cfg[:4].eq(self.rtlink.o.data),
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0x22: header.cfg.eq(self.rtlink.o.data),
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# leds
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0x23: self.serializer.cfg[4:12].eq(self.rtlink.o.data),
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0x23: header.leds.eq(self.rtlink.o.data),
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# reserved
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0x24: self.serializer.cfg[12:].eq(self.rtlink.o.data),
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0x24: header.reserved.eq(self.rtlink.o.data),
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}
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for i in range(0, len(self.serializer.dacs), width):
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for i in range(0, len(dacs), width):
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cases[i] = [
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Cat(self.serializer.dacs[i:i + width]).eq(self.rtlink.o.data),
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Cat(dacs[i:i + width]).eq(self.rtlink.o.data),
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[If(~hold[i + j],
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self.serializer.enable[i + j].eq(1),
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header.enable[i + j].eq(1),
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) for j in range(width)]
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]
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self.sync.rio_phy += [
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If(self.serializer.stb,
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self.serializer.enable.eq(0),
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header.enable.eq(0),
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read_regs[header.addr].eq(self.serializer.readback),
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header.addr.eq(header.addr + 1),
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),
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If(self.rtlink.o.stb & ~self.rtlink.o.address[-1],
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Case(self.rtlink.o.address[:-1], cases),
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