forked from M-Labs/artiq
sayma_amc: enable DRTIO switching
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parent
0cf8a46bbd
commit
6cb0f5de59
@ -358,27 +358,58 @@ class Satellite(BaseSoC, RTMCommon):
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
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self.submodules.drtiosat = rx0(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[0],
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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drtiorep_csr_group = []
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drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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if i == 0:
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
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core = cdr(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[i],
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self.rx_synchronizer))
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self.submodules.drtiosat = core
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self.csr_devices.append("drtiosat")
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self.submodules.drtioaux0 = rx0(DRTIOAuxController(
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self.drtiosat.link_layer))
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self.csr_devices.append("drtioaux0")
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self.add_wb_slave(self.mem_map["drtioaux"], 0x800,
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self.drtioaux0.bus)
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self.add_memory_region("drtioaux0_mem", self.mem_map["drtioaux"] | self.shadow_base, 0x800)
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else:
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corerep_name = "drtiorep" + str(i-1)
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drtiorep_csr_group.append(corerep_name)
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core = cdr(DRTIORepeater(
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self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, corerep_name, core)
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drtio_cri.append(core.cri)
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self.csr_devices.append(corerep_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtioaux", ["drtioaux0"])
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self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
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self.comb += [
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self.drtiosat.cri.connect(self.local_io.cri),
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self.drtiosat.async_errors.eq(self.local_io.async_errors),
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]
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self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.drtiosat.cri],
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[self.local_io.cri] + drtio_cri,
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mode="sync", enable_routing=True)
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self.csr_devices.append("cri_con")
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self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
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self.csr_devices.append("routing_table")
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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if self.hw_rev == "v2.0":
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