occheung/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

sayma_amc2: select filtered clock from Si5324

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2019-10-04 21:28:26 +08:00
parent 6f533727cb
commit 0cf8a46bbd
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/targets/sayma_amc.py
View File

@ -381,6 +381,8 @@ class Satellite(BaseSoC, RTMCommon):
]
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
if self.hw_rev == "v2.0":
self.comb += platform.request("filtered_clk_sel").eq(1)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,