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phaser: work around for unreliable transciever init

This commit is contained in:
Robert Jördens 2016-10-16 16:01:23 +02:00
parent 0259c80015
commit 6a683c712b
1 changed files with 14 additions and 0 deletions
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14
artiq/examples/phaser/repository/dac_setup.py
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@ -34,6 +34,19 @@ class DACSetup(EnvExperiment):
@kernel @kernel
def run(self): def run(self):
# TODO; remove when
# https://github.com/m-labs/jesd204b/issues/6
# is resolved
for i in range(99):
try:
self.cfg()
return
except:
pass
self.cfg()
@kernel
def cfg(self):
self.core.reset() self.core.reset()
self.ad9154.jesd_enable(0) self.ad9154.jesd_enable(0)
self.ad9154.jesd_prbs(0) self.ad9154.jesd_prbs(0)
@ -48,6 +61,7 @@ class DACSetup(EnvExperiment):
self.monitor() self.monitor()
while not self.ad9154.jesd_ready(): while not self.ad9154.jesd_ready():
pass pass
self.busywait_us(10000)
if self.ad9154.dac_read(AD9154_CODEGRPSYNCFLG) != 0x0f: if self.ad9154.dac_read(AD9154_CODEGRPSYNCFLG) != 0x0f:
raise ValueError("bad CODEGRPSYNCFLG") raise ValueError("bad CODEGRPSYNCFLG")
self.core.break_realtime() self.core.break_realtime()