From 6a683c712b8a44e6416f415f8a005b35b1bd4705 Mon Sep 17 00:00:00 2001
From: Robert Jordens <rj@m-labs.hk>
Date: Sun, 16 Oct 2016 16:01:23 +0200
Subject: [PATCH] phaser: work around for unreliable transciever init

---
 artiq/examples/phaser/repository/dac_setup.py | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/artiq/examples/phaser/repository/dac_setup.py b/artiq/examples/phaser/repository/dac_setup.py
index 3a1693ecb..ed9a2da76 100644
--- a/artiq/examples/phaser/repository/dac_setup.py
+++ b/artiq/examples/phaser/repository/dac_setup.py
@@ -34,6 +34,19 @@ class DACSetup(EnvExperiment):
 
     @kernel
     def run(self):
+        # TODO; remove when
+        # https://github.com/m-labs/jesd204b/issues/6
+        # is resolved
+        for i in range(99):
+            try:
+                self.cfg()
+                return
+            except:
+                pass
+        self.cfg()
+
+    @kernel
+    def cfg(self):
         self.core.reset()
         self.ad9154.jesd_enable(0)
         self.ad9154.jesd_prbs(0)
@@ -48,6 +61,7 @@ class DACSetup(EnvExperiment):
         self.monitor()
         while not self.ad9154.jesd_ready():
             pass
+        self.busywait_us(10000)
         if self.ad9154.dac_read(AD9154_CODEGRPSYNCFLG) != 0x0f:
             raise ValueError("bad CODEGRPSYNCFLG")
         self.core.break_realtime()