occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

transforms.interleaver: don't fail on degenerate parallel blocks.

This commit is contained in:
whitequark 2015-12-16 15:41:58 +08:00
parent 4def561710
commit 69cdeaf706
1 changed files with 9 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
artiq/compiler/transforms/interleaver.py
View File

@ -104,15 +104,17 @@ class Interleaver:
target_terminator = target_block.terminator()
if isinstance(target_terminator, ir.Parallel):
target_terminator.replace_with(ir.Branch(source_block))
else:
assert isinstance(target_terminator, (ir.Delay, ir.Branch))
elif isinstance(target_terminator, (ir.Delay, ir.Branch)):
target_terminator.set_target(source_block)
else:
assert False
source_terminator = source_block.terminator()
if not isinstance(source_terminator, ir.Delay):
if isinstance(source_terminator, (ir.Parallel, ir.Branch)):
source_terminator.replace_with(ir.Branch(source_terminator.target()))
else:
elif isinstance(source_terminator, ir.Return):
break
elif isinstance(source_terminator, ir.Delay):
old_decomp = source_terminator.decomposition()
if is_pure_delay(old_decomp):
if target_time_delta > 0:
@ -144,6 +146,8 @@ class Interleaver:
source_terminator.interval = iodelay.Const(target_time_delta)
else:
source_terminator.replace_with(ir.Branch(source_terminator.target()))
else:
assert False
target_block = source_block
target_time = new_target_time