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targets: integrate RTIO analyzer

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This commit is contained in:
Sebastien Bourdeauducq 2015-12-16 17:36:52 +08:00
parent afaad270cc
commit 4def561710
2 changed files with 8 additions and 4 deletions
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6
artiq/gateware/targets/kc705.py
View File

@ -85,7 +85,8 @@ class _NIST_QCx(MiniSoC, AMPSoC):
"rtio": None, # mapped on Wishbone instead
"rtio_crg": 13,
"kernel_cpu": 14,
"rtio_moninj": 15
"rtio_moninj": 15,
"rtio_analyzer": 16
}
csr_map.update(MiniSoC.csr_map)
mem_map = {
@ -138,6 +139,9 @@ TIMESPEC "TSfix_cdc2" = FROM "GRPrio_clk" TO "GRPrsys_clk" TIG;
self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
rtio_csrs)
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
self.get_native_sdram_if())
class NIST_QC1(_NIST_QCx):
def __init__(self, cpu_type="or1k", **kwargs):

6
artiq/gateware/targets/pipistrello.py
View File

@ -104,9 +104,9 @@ TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
class NIST_QC1(BaseSoC, AMPSoC):
csr_map = {
"rtio": None, # mapped on Wishbone instead
"rtio_crg": 13,
"kernel_cpu": 14,
"rtio_moninj": 15
"rtio_crg": 10,
"kernel_cpu": 11,
"rtio_moninj": 12
}
csr_map.update(BaseSoC.csr_map)
mem_map = {