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ttl: improve clockgen doc

This commit is contained in:
Sebastien Bourdeauducq 2015-07-05 19:07:13 +02:00
parent 2eeaa3b9be
commit 58c0150822
2 changed files with 5 additions and 0 deletions
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4
artiq/coredevice/ttl.py
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@ -253,6 +253,10 @@ class TTLClockGen(AutoDB):
accumulator is connected to the TTL line. Setting the frequency tuning accumulator is connected to the TTL line. Setting the frequency tuning
word has the additional effect of setting the phase accumulator to word has the additional effect of setting the phase accumulator to
0x800000. 0x800000.
Due to the way the clock generator operates, frequency tuning words
that are not powers of two cause jitter of one RTIO clock cycle at the
output.
""" """
syscall("ttl_clock_set", now_mu(), self.channel, frequency) syscall("ttl_clock_set", now_mu(), self.channel, frequency)
self.previous_timestamp = now_mu() self.previous_timestamp = now_mu()

1
artiq/gateware/rtio/phy/ttl_simple.py
View File

@ -89,6 +89,7 @@ class ClockGen(Module):
self.sync.rio += If(self.rtlink.o.stb, ftw.eq(self.rtlink.o.data)) self.sync.rio += If(self.rtlink.o.stb, ftw.eq(self.rtlink.o.data))
self.sync.rio_phy += [ self.sync.rio_phy += [
acc.eq(acc + ftw), acc.eq(acc + ftw),
# rtlink takes precedence over regular acc increments
If(self.rtlink.o.stb, If(self.rtlink.o.stb,
If(self.rtlink.o.data != 0, If(self.rtlink.o.data != 0,
# known phase on frequency write: at rising edge # known phase on frequency write: at rising edge