From 58c01508226e721b7f016747b18ff289fb928514 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 5 Jul 2015 19:07:13 +0200 Subject: [PATCH] ttl: improve clockgen doc --- artiq/coredevice/ttl.py | 4 ++++ artiq/gateware/rtio/phy/ttl_simple.py | 1 + 2 files changed, 5 insertions(+) diff --git a/artiq/coredevice/ttl.py b/artiq/coredevice/ttl.py index 431958fb7..d65aa62ff 100644 --- a/artiq/coredevice/ttl.py +++ b/artiq/coredevice/ttl.py @@ -253,6 +253,10 @@ class TTLClockGen(AutoDB): accumulator is connected to the TTL line. Setting the frequency tuning word has the additional effect of setting the phase accumulator to 0x800000. + + Due to the way the clock generator operates, frequency tuning words + that are not powers of two cause jitter of one RTIO clock cycle at the + output. """ syscall("ttl_clock_set", now_mu(), self.channel, frequency) self.previous_timestamp = now_mu() diff --git a/artiq/gateware/rtio/phy/ttl_simple.py b/artiq/gateware/rtio/phy/ttl_simple.py index 0127d19a0..d424babe7 100644 --- a/artiq/gateware/rtio/phy/ttl_simple.py +++ b/artiq/gateware/rtio/phy/ttl_simple.py @@ -89,6 +89,7 @@ class ClockGen(Module): self.sync.rio += If(self.rtlink.o.stb, ftw.eq(self.rtlink.o.data)) self.sync.rio_phy += [ acc.eq(acc + ftw), + # rtlink takes precedence over regular acc increments If(self.rtlink.o.stb, If(self.rtlink.o.data != 0, # known phase on frequency write: at rising edge