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firmware: Add Si5324 config for 125 MHz ext ref

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PLL divider settings as suggested by DSPLLsim 5.1.
This commit is contained in:
David Nadlinger 2019-04-15 22:20:30 +01:00
parent dc7a642b26
commit 4d215cf541
2 changed files with 17 additions and 2 deletions
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17
artiq/firmware/runtime/main.rs
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@ -137,8 +137,8 @@ fn startup() {
#[cfg(si5324_as_synthesizer)] #[cfg(si5324_as_synthesizer)]
fn setup_si5324_as_synthesizer() fn setup_si5324_as_synthesizer()
{ {
// 125MHz output, from 100MHz CLKIN2 reference, 586 Hz // 125MHz output, from 100MHz CLKIN2 reference, 586 Hz loop bandwidth
#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", si5324_ext_ref))] #[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "100.0"))]
const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
= board_artiq::si5324::FrequencySettings { = board_artiq::si5324::FrequencySettings {
n1_hs : 10, n1_hs : 10,
@ -150,6 +150,19 @@ fn setup_si5324_as_synthesizer()
bwsel : 4, bwsel : 4,
crystal_ref: false crystal_ref: false
}; };
// 125MHz output, from 125MHz CLKIN2 reference, 606 Hz loop bandwidth
#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "125.0"))]
const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings
= board_artiq::si5324::FrequencySettings {
n1_hs : 5,
nc1_ls : 8,
n2_hs : 7,
n2_ls : 360,
n31 : 63,
n32 : 63,
bwsel : 4,
crystal_ref: false
};
// 125MHz output, from crystal, 7 Hz // 125MHz output, from crystal, 7 Hz
#[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", not(si5324_ext_ref)))] #[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", not(si5324_ext_ref)))]
const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings

2
artiq/gateware/targets/kasli.py
View File

@ -159,6 +159,7 @@ class Opticlock(StandaloneBase):
self.config["SI5324_AS_SYNTHESIZER"] = None self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["SI5324_EXT_REF"] = None self.config["SI5324_EXT_REF"] = None
self.config["EXT_REF_FREQUENCY"] = "100.0"
self.config["RTIO_FREQUENCY"] = "125.0" self.config["RTIO_FREQUENCY"] = "125.0"
if hw_rev == "v1.0": if hw_rev == "v1.0":
# EEM clock fan-out from Si5324, not MMCX # EEM clock fan-out from Si5324, not MMCX
@ -291,6 +292,7 @@ class PTB2(StandaloneBase):
self.config["SI5324_AS_SYNTHESIZER"] = None self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["SI5324_EXT_REF"] = None self.config["SI5324_EXT_REF"] = None
self.config["EXT_REF_FREQUENCY"] = "100.0"
self.config["RTIO_FREQUENCY"] = "125.0" self.config["RTIO_FREQUENCY"] = "125.0"
if hw_rev == "v1.0": if hw_rev == "v1.0":
# EEM clock fan-out from Si5324, not MMCX # EEM clock fan-out from Si5324, not MMCX