From 4d215cf541bedf6380b0e956f9bedfd8a20d5fad Mon Sep 17 00:00:00 2001 From: David Nadlinger Date: Mon, 15 Apr 2019 22:20:30 +0100 Subject: [PATCH] firmware: Add Si5324 config for 125 MHz ext ref PLL divider settings as suggested by DSPLLsim 5.1. --- artiq/firmware/runtime/main.rs | 17 +++++++++++++++-- artiq/gateware/targets/kasli.py | 2 ++ 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/artiq/firmware/runtime/main.rs b/artiq/firmware/runtime/main.rs index cc86c2217..6708da977 100644 --- a/artiq/firmware/runtime/main.rs +++ b/artiq/firmware/runtime/main.rs @@ -137,8 +137,8 @@ fn startup() { #[cfg(si5324_as_synthesizer)] fn setup_si5324_as_synthesizer() { - // 125MHz output, from 100MHz CLKIN2 reference, 586 Hz - #[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", si5324_ext_ref))] + // 125MHz output, from 100MHz CLKIN2 reference, 586 Hz loop bandwidth + #[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "100.0"))] const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings = board_artiq::si5324::FrequencySettings { n1_hs : 10, @@ -150,6 +150,19 @@ fn setup_si5324_as_synthesizer() bwsel : 4, crystal_ref: false }; + // 125MHz output, from 125MHz CLKIN2 reference, 606 Hz loop bandwidth + #[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", si5324_ext_ref, ext_ref_frequency = "125.0"))] + const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings + = board_artiq::si5324::FrequencySettings { + n1_hs : 5, + nc1_ls : 8, + n2_hs : 7, + n2_ls : 360, + n31 : 63, + n32 : 63, + bwsel : 4, + crystal_ref: false + }; // 125MHz output, from crystal, 7 Hz #[cfg(all(not(si5324_sayma_ref), rtio_frequency = "125.0", not(si5324_ext_ref)))] const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 716c83dc4..04c990343 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -159,6 +159,7 @@ class Opticlock(StandaloneBase): self.config["SI5324_AS_SYNTHESIZER"] = None self.config["SI5324_EXT_REF"] = None + self.config["EXT_REF_FREQUENCY"] = "100.0" self.config["RTIO_FREQUENCY"] = "125.0" if hw_rev == "v1.0": # EEM clock fan-out from Si5324, not MMCX @@ -291,6 +292,7 @@ class PTB2(StandaloneBase): self.config["SI5324_AS_SYNTHESIZER"] = None self.config["SI5324_EXT_REF"] = None + self.config["EXT_REF_FREQUENCY"] = "100.0" self.config["RTIO_FREQUENCY"] = "125.0" if hw_rev == "v1.0": # EEM clock fan-out from Si5324, not MMCX