forked from M-Labs/artiq
suservo: use BUFIO/BUFH for ADC
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e36deab0a8
commit
4903eb074c
@ -119,9 +119,16 @@ class ADC(Module, DiffMixin):
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except AttributeError:
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sck_en_ret = 1
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self.clock_domains.cd_ret = ClockDomain("ret", reset_less=True)
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clkout = self._diff(pads, "clkout")
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clkout_fabric = Signal()
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clkout_io = Signal()
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self.specials += [
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Instance("BUFH", i_I=clkout, o_O=clkout_fabric),
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Instance("BUFIO", i_I=clkout, o_O=clkout_io)
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]
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self.comb += [
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# falling clkout makes two bits available
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self.cd_ret.clk.eq(~self._diff(pads, "clkout")),
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self.cd_ret.clk.eq(~clkout_fabric)
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]
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k = p.channels//p.lanes
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assert 2*t_read == k*p.width
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@ -130,7 +137,7 @@ class ADC(Module, DiffMixin):
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sdo_sr1 = Signal(t_read - 1)
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sdo_ddr = Signal(2)
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self.specials += io.DDRInput(sdo, sdo_ddr[1], sdo_ddr[0],
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self.cd_ret.clk)
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~clkout_io)
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self.sync.ret += [
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If(self.reading & sck_en_ret,
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sdo_sr0.eq(Cat(sdo_ddr[0], sdo_sr0)),
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