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phaser: fix oscillator rtio address for even base addresses 

close #1580
This commit is contained in:
Robert Jördens 2021-01-19 16:56:45 +01:00
parent 641f8bcdd6
commit 261870bdee
1 changed files with 1 additions and 1 deletions
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2
artiq/coredevice/phaser.py
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@ -928,7 +928,7 @@ class PhaserOscillator:
:param clr: Clear the phase accumulator (persistent)
"""
data = (asf & 0x7fff) | ((clr & 1) << 15) | (pow << 16)
rtio_output(self.base_addr | (1 << 8), data)
rtio_output(self.base_addr + (1 << 8), data)
@kernel
def set_amplitude_phase(self, amplitude, phase=0., clr=0):