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4 Commits

Author SHA1 Message Date
occheung 9d3d73479a spi: add delay margin 2021-01-18 14:35:17 +08:00
occheung bcb3eef8cd lib: derive debug for error for unwrapping 2021-01-18 14:00:37 +08:00
occheung 500c855d00 spi: add CS delay to accomodate booster 2021-01-18 13:59:39 +08:00
occheung 1a2c22cfb2 lib: reduce stack usage 2021-01-18 13:58:07 +08:00
2 changed files with 6 additions and 1 deletions

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@ -16,7 +16,7 @@ pub mod tx;
pub mod smoltcp_phy; pub mod smoltcp_phy;
/// Max raw frame array size /// Max raw frame array size
pub const RAW_FRAME_LENGTH_MAX: usize = 0x1000; pub const RAW_FRAME_LENGTH_MAX: usize = 1518;
pub trait EthController { pub trait EthController {
fn init_dev(&mut self, delay: &mut impl DelayUs<u16>) -> Result<(), EthControllerError>; fn init_dev(&mut self, delay: &mut impl DelayUs<u16>) -> Result<(), EthControllerError>;
@ -29,6 +29,7 @@ pub trait EthController {
} }
/// TODO: Improve these error types /// TODO: Improve these error types
#[derive(Debug)]
pub enum EthControllerError { pub enum EthControllerError {
SpiPortError, SpiPortError,
GeneralError, GeneralError,

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@ -131,13 +131,17 @@ impl <SPI: Transfer<u8>,
match self.spi.transfer(&mut buf) { match self.spi.transfer(&mut buf) {
Ok(_) => { Ok(_) => {
// Disable chip select // Disable chip select
cortex_m::asm::delay(10_u32);
self.nss.set_high(); self.nss.set_high();
cortex_m::asm::delay(5_u32);
Ok(buf[2]) Ok(buf[2])
}, },
// TODO: Maybe too naive? // TODO: Maybe too naive?
Err(_) => { Err(_) => {
// Disable chip select // Disable chip select
cortex_m::asm::delay(10_u32);
self.nss.set_high(); self.nss.set_high();
cortex_m::asm::delay(5_u32);
Err(SpiPortError::TransferError) Err(SpiPortError::TransferError)
} }
} }