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zynq-rs
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31 Commits

Author SHA1 Message Date
newell eae21579bc More updates. Fixed openocd. 2024-09-04 16:05:55 -07:00
newell a75568bd42 EBAZ4205 Initial commit 2024-08-13 14:01:46 -07:00
Astro a3eabf1947 libboard_zynq: prepare target_kasli_soc 2020-11-19 19:28:17 +01:00
Astro a32d7abb9a libboard_zynq: rename ddr DCI_FREQ to DCI_MAX_FREQ 2020-11-19 19:21:38 +01:00
Astro 0714162113 rename target_cora_z7_10 to target_coraz7 globally 2020-11-13 17:56:47 +01:00
Astro 0a40d4f36d libboard_zynq: fix zc706 build 2020-11-13 00:23:38 +01:00
Astro 990fa56d6a libboard_zynq: complete ddr without ps7_init for redpitaya 2020-11-13 00:10:34 +01:00
Astro 07fedddad9 libboard_zynq: doc ddr size limitation, correct target_redpitaya to 512MB 2020-11-11 13:25:55 +01:00
Astro dffe3cb251 libboard_zynq: rm superfluous ddr settings for cora_z7_10 2020-11-10 20:53:46 +01:00
Astro b9323653bb libboard_zynq: complete ddr without ps7_init for cora_z7_10 2020-11-10 14:33:31 +01:00
Astro 515d3bb381 libboard_zynq: configure ddr while keeping rstb low 2020-11-08 22:47:59 +01:00
Astro e508b78b3e libboard_zynq: add ps7_init for cora_z7_10 2020-11-08 19:28:59 +01:00
pca006132 f60d0589cc fix ps7_init compilation error and warnings 2020-10-01 00:17:47 +08:00
pca006132 6af453494b libboard_zynq/ddr: use ps7_init for redpitaya ddr 2020-09-26 17:01:37 +08:00
Sebastien Bourdeauducq a6955edf14 add Red Pitaya support (WIP) 2020-09-09 20:10:05 +08:00
Sebastien Bourdeauducq 66c66447dd fix some compilation warnings 2020-09-06 00:17:59 +08:00
Harry Ho 1a96a7550a libboard_zynq: make RegisterBlock constructors more consistent 2020-08-13 14:49:26 +08:00
Harry Ho 36947104e3 libboard_zynq: make constructor names more consistent 2020-08-13 13:31:53 +08:00
Astro ef4fb598fb ddr: improve dci divisors calculation 2020-07-28 00:43:33 +02:00
Astro e4e7141bf3 ddr: delint 2020-07-06 19:46:18 +02:00
pca006132 90904634cd DDR: fixed register write. 
Previously it writes `0x20066`, while the ps7_init set it to be
`0x200066`, notice the 1 more 0.
This should perform the same writes to the registers, so we do not have
to apply the ps7_init in artiq_zynq.
 2020-07-06 11:46:37 +08:00
Astro f0697c3ec3 ddr: implement additional configuration 2020-07-03 02:20:10 +02:00
Astro b2c707d543 ddr: remove superfluous `_reg` from register names 2020-07-03 02:20:10 +02:00
Astro 3841accd9c libboard_zynq: fix ddr memtest range 2020-05-09 02:53:58 +02:00
Astro 3e02980c20 libboard_zynq: fix access to "full" 1022 MB on target_zc706 2020-05-09 02:35:39 +02:00
Sebastien Bourdeauducq e047c2900b ddr: log clock info with debug level 2020-05-01 12:27:43 +08:00
Astro 877f2c34bd libboard_zynq: use log logging 2020-05-01 01:46:42 +02:00
Astro 8a98cef3fc libboard_zynq: fix some hw setup 2020-04-03 00:17:25 +02:00
Astro ed52ead914 cora ddr attempts 2020-03-28 21:50:06 +01:00
Astro aae85981e2 libboard_zynq::clocks: setup clock sources and cpu clock 2020-01-23 23:15:10 +01:00
Astro cf1983e543 split into lib{register, cortex_a9, board_zynq, board_zc706} crates 2019-12-17 23:35:58 +01:00