newell
/
zynq-rs
forked from M-Labs/zynq-rs
1
0
Fork 0
Code Pull Requests Activity

libboard_zynq: fix access to "full" 1022 MB on target_zc706

This commit is contained in:
Astro 2020-05-09 02:32:29 +02:00
parent 66cd0c7630
commit 3e02980c20
1 changed files with 11 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
libboard_zynq/src/ddr/mod.rs
View File

@ -183,6 +183,14 @@ impl DdrRam {
/// Reset DDR controller
fn reset_ddrc(&mut self) {
#[cfg(feature = "target_zc706")]
unsafe {
// row/column address bits
self.regs.dram_addr_map_bank.write(0x00000777);
self.regs.dram_addr_map_col.write(0xFFF00000);
self.regs.dram_addr_map_row.write(0x0F666666);
}
#[cfg(feature = "target_zc706")]
let width = regs::DataBusWidth::Width32bit;
#[cfg(feature = "target_cora_z7_10")]
@ -209,9 +217,11 @@ impl DdrRam {
0x0010_0000 as *mut _
}
/// actually there's 1 MB more but starting at 0x0000_0000
/// overlaps with OCM.
pub fn size(&self) -> usize {
#[cfg(feature = "target_zc706")]
let megabytes = 511;
let megabytes = 1022;
#[cfg(feature = "target_cora_z7_10")]
let megabytes = 511;