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a17a5d2925
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sdcard: Changed some debug to trace.
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2020-06-15 16:54:30 +08:00 |
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e0f26871db
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devc working!
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2020-06-15 16:07:31 +08:00 |
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82ec1ba7a7
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sdio: better logging
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2020-06-13 16:31:25 +08:00 |
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d3b488bfb3
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standard capacity support
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2020-06-11 10:21:01 +08:00 |
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074b3547de
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sdio: fix unsound MaybeUninit usage
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2020-06-11 10:07:19 +08:00 |
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316ea61702
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sdio: move ADMA2_DESCR32_TABLE into SdCard
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2020-06-11 10:07:19 +08:00 |
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1586190712
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sdio: turn Adma2Desc32.attribute into a register!
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2020-06-11 10:07:19 +08:00 |
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32349e9dec
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sdio: convert Adma2Desc32 to VolatileCells, make ADMA2_DESCR32_TABLE: MaybeUninit
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2020-06-11 10:07:19 +08:00 |
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b942cdcbc8
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sdio: change Adma2Desc32 alignment from 1 to 4
this should not break anything.
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2020-06-11 10:07:19 +08:00 |
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a1a211334f
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eth: always just allocate desc list + buffers
buffers are allocated vec anyway. this removes the lifetime hack and
further prepares work on cache-line alignment to enable L1 writeback.
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2020-06-11 00:21:18 +02:00 |
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cf17a1c60a
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removed unneeded methods
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2020-06-10 12:55:22 +08:00 |
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5332587de6
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Changed mutability
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2020-06-10 12:54:50 +08:00 |
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0ebc4a61c8
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Modified SDIO to handle u8 buffer instead of u32.
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2020-06-09 17:03:17 +08:00 |
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236592ae66
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SDIO module completed
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2020-06-05 12:27:12 +08:00 |
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2c82fb793e
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Merge pull request 'sdio-registers' (#29)
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2020-05-15 06:44:32 +08:00 |
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0c48dd934e
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libboard_zynq: fix sclr::ddriob_ddr_ctrl vref_int_en
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2020-05-10 22:14:55 +02:00 |
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3841accd9c
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libboard_zynq: fix ddr memtest range
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2020-05-09 02:53:58 +02:00 |
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3e02980c20
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libboard_zynq: fix access to "full" 1022 MB on target_zc706
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2020-05-09 02:35:39 +02:00 |
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73b0ec9837
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fixed typo
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2020-05-06 13:58:46 +08:00 |
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4acee21c05
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Merge branch 'master' of git.m-labs.hk:M-Labs/zc706 into sdio-registers
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2020-05-06 11:06:38 +08:00 |
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ce844f1b02
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devc: add is_done()
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2020-05-04 22:16:53 +08:00 |
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c955eaae7f
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libboard_zynq: flush Uart by waiting for tx idle
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2020-05-02 23:32:01 +02:00 |
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0f666c570c
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libboard_zynq: remove unneeded Uart flush
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2020-05-02 23:30:45 +02:00 |
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244ccdeac2
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finished register definitions
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2020-05-01 15:38:07 +08:00 |
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e047c2900b
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ddr: log clock info with debug level
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2020-05-01 12:27:43 +08:00 |
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877f2c34bd
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libboard_zynq: use log logging
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2020-05-01 01:46:42 +02:00 |
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619ebf147c
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libsupport_zynq: move mod logger to libboard_zynq
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2020-05-01 01:33:40 +02:00 |
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0d4d021b1b
|
clean up
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2020-05-01 01:17:53 +02:00 |
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d9e8a667bd
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some macro changes and more registers
|
2020-04-29 21:19:24 +08:00 |
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b22cc4e2b6
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various control registers
|
2020-04-29 09:34:17 +08:00 |
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3238dae99f
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started writing register definitions
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2020-04-28 23:00:47 +08:00 |
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aa93794632
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libboard_zynq: add GlobalTimer::get_us(), use in libsupport_zynq::logger
|
2020-04-25 03:01:19 +02:00 |
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fe6a058a6b
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libboard_zynq: find prescaler for GlobalTimer, rename new() to start()
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2020-04-25 02:59:48 +02:00 |
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88a2a2bc71
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libasync, libboard_zynq: add block_async glue, make GlobalTimer sharable
|
2020-04-25 01:18:49 +02:00 |
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8012573a8f
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libboard_zynq: impl embedded_hal CountDown for GlobalTimer
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2020-04-25 00:44:32 +02:00 |
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4ab6fb6271
|
libboard_zynq: use Void in uart embedded_hal impl
|
2020-04-25 00:28:17 +02:00 |
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f835192c0a
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libboard_zynq: add GlobalTimer implementation
|
2020-04-25 00:18:45 +02:00 |
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04c47b9bdb
|
libboard_zynq: impl embedded_hal serial write traits for Uart
|
2020-04-24 21:31:37 +02:00 |
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f8782f3f69
|
libboard_zynq: let println!() write no '\r'
|
2020-04-20 23:44:16 +02:00 |
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4b346f5c55
|
libboard_zynq: fix flash manual_mode chip_index
|
2020-04-10 20:41:16 +02:00 |
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2dda3ca4e6
|
libboard_zynq: delint
|
2020-04-10 20:41:16 +02:00 |
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c3ebafa6ed
|
libboard_zynq: fix flash read
|
2020-04-06 22:41:49 +02:00 |
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8a98cef3fc
|
libboard_zynq: fix some hw setup
|
2020-04-03 00:17:25 +02:00 |
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46af38906e
|
libboard_zynq: wrap eth Buffer for alignment
|
2020-03-29 00:08:43 +01:00 |
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ed52ead914
|
cora ddr attempts
|
2020-03-28 21:50:06 +01:00 |
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319f7d9eef
|
move smoltcp dependency to libboard_zynq only
|
2020-03-25 22:23:30 +01:00 |
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29bf29a037
|
add some fpga regs
|
2020-03-25 13:02:01 +01:00 |
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03da85dcea
|
libboard_zynq::dmac: enable mod, add channel_regs()
|
2020-02-03 23:04:26 +01:00 |
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d7e8ba297b
|
libboard_zynq::dmac: unify equal registers
|
2020-02-03 22:11:44 +01:00 |
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f9cb2e7cb0
|
delint
|
2020-01-30 23:18:14 +01:00 |
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