|
|
85bd506132
|
zynq::ddr: parameters
|
2019-10-27 20:38:06 +01:00 |
|
|
|
9b4f07f37c
|
zynq::ddr, main: parameters, memtest
|
2019-10-25 23:19:34 +02:00 |
|
|
|
a4d3360a70
|
zynq::slcr: implement Display for PllStatus
|
2019-10-25 20:38:10 +02:00 |
|
|
|
838434cdec
|
zynq::ddr: wait for init
|
2019-10-25 19:15:22 +02:00 |
|
|
|
4cf5283ba8
|
zynq::ddr: implement reset_ddrc(), add to main
|
2019-10-24 01:39:14 +02:00 |
|
|
|
a8886de067
|
zynq::ddr: implement configure_iob()
|
2019-10-24 01:24:12 +02:00 |
|
|
|
afda48e3fe
|
zynq::ddr: add clock_setup(), calibrate_iob_impedance()
|
2019-10-22 01:25:35 +02:00 |
|
|
|
c046bbf8a2
|
move slcr, clocks, uart, eth into src/zynq/
|
2019-10-21 22:19:03 +02:00 |
|
|
|
9d725bcf0f
|
zynq::ddr: init with clock setup
|
2019-10-21 22:12:10 +02:00 |
|
