8 Commits

Author	SHA1	Message	Date
Astro	ef6d0ff3f1	boot: reset core1 before start	2019-11-18 00:38:03 +01:00
Astro	eb56dda44f	zynq::slcr::unlocked: fix comment	2019-11-07 00:13:50 +01:00
Astro	04e816d99e	zynq::slcr: fix a bitfield index ... that didn't solve our problems.	2019-11-03 02:01:42 +01:00
Astro	e61d1268ac	zynq::slcr: doc, fix	2019-10-25 23:18:18 +02:00
Astro	a4d3360a70	zynq::slcr: implement Display for PllStatus	2019-10-25 20:38:10 +02:00
Astro	a8886de067	zynq::ddr: implement configure_iob()	2019-10-24 01:24:12 +02:00
Astro	afda48e3fe	zynq::ddr: add clock_setup(), calibrate_iob_impedance()	2019-10-22 01:25:35 +02:00
Astro	c046bbf8a2	move slcr, clocks, uart, eth into src/zynq/	2019-10-21 22:19:03 +02:00