5 Commits

Author	SHA1	Message	Date
Astro	85bd506132	zynq::ddr: parameters	2019-10-27 20:38:06 +01:00
Astro	27114aec62	zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage ... this seems to make DDR RAM work.	2019-10-27 20:30:56 +01:00
Astro	9b4f07f37c	zynq::ddr, main: parameters, memtest	2019-10-25 23:19:34 +02:00
Astro	a4d3360a70	zynq::slcr: implement Display for PllStatus	2019-10-25 20:38:10 +02:00
Astro	c046bbf8a2	move slcr, clocks, uart, eth into src/zynq/	2019-10-21 22:19:03 +02:00