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zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage

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this seems to make DDR RAM work.
This commit is contained in:
Astro 2019-10-27 20:30:38 +01:00
parent 9b4f07f37c
commit 27114aec62
1 changed files with 1 additions and 1 deletions
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src/zynq/clocks.rs
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@ -102,7 +102,7 @@ impl CpuClocks {
);
let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
.filter(|(fdiv_max, _)| fdiv <= *fdiv_max)
.last()
.nth(0)
.expect("PLL_FDIV_LOCK_PARAM")
.1.clone();
regs.ddr_pll_cfg.write(