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zynq-rs
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More updates. Fixed openocd.

This commit is contained in:
newell 2024-09-04 16:05:55 -07:00
parent a75568bd42
commit eae21579bc
4 changed files with 11 additions and 5 deletions
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3
libboard_zynq/src/ddr/mod.rs
View File

@ -478,11 +478,12 @@ impl DdrRam {
let megabytes = 1023; let megabytes = 1023;
#[cfg(any( #[cfg(any(
feature = "target_coraz7", feature = "target_coraz7",
feature = "target_ebaz4205",
feature = "target_redpitaya", feature = "target_redpitaya",
feature = "target_kasli_soc", feature = "target_kasli_soc",
))] ))]
let megabytes = 512; let megabytes = 512;
#[cfg(feature = "target_ebaz4205")]
let megabytes = 256;
megabytes * 1024 * 1024 megabytes * 1024 * 1024
} }

2
libboard_zynq/src/eth/mod.rs
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@ -154,6 +154,8 @@ pub struct Eth<GEM: Gem, RX, TX> {
impl Eth<Gem0, (), ()> { impl Eth<Gem0, (), ()> {
pub fn eth0(macaddr: [u8; 6]) -> Self { pub fn eth0(macaddr: [u8; 6]) -> Self {
// EBAZ4205 ETH uses EMIO
#[cfg(not(feature = "target_ebaz4205"))]
slcr::RegisterBlock::unlocked(|slcr| { slcr::RegisterBlock::unlocked(|slcr| {
// Manual example: 0x0000_1280 // Manual example: 0x0000_1280
// MDIO // MDIO

2
openocd/ebaz4205.cfg
View File

@ -4,7 +4,7 @@ adapter driver ftdi
ftdi vid_pid 0x0403 0x6010 ftdi vid_pid 0x0403 0x6010
ftdi channel 0 ftdi channel 0
# Every pin set as high impedance except TCK, TDI, TDO and TMS # Every pin set as high impedance except TCK, TDI, TDO and TMS
ftdi layout_init 0x0008 0x000b ftdi layout_init 0x0088 0x008b
# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip) # nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
# This choice is arbitrary. Use other GPIO pin if desired. # This choice is arbitrary. Use other GPIO pin if desired.

5
szl/src/main.rs
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@ -80,12 +80,15 @@ pub fn main_core0() {
); );
info!("Simple Zynq Loader starting..."); info!("Simple Zynq Loader starting...");
#[cfg(not(feature = "target_kasli_soc"))] #[cfg(not(any(feature = "target_kasli_soc", feature = "target_ebaz4205")))]
const CPU_FREQ: u32 = 800_000_000; const CPU_FREQ: u32 = 800_000_000;
#[cfg(feature = "target_kasli_soc")] #[cfg(feature = "target_kasli_soc")]
const CPU_FREQ: u32 = 1_000_000_000; const CPU_FREQ: u32 = 1_000_000_000;
#[cfg(feature = "target_ebaz4205")]
const CPU_FREQ: u32 = 666_666_666;
ArmPll::setup(2 * CPU_FREQ); ArmPll::setup(2 * CPU_FREQ);
Clocks::set_cpu_freq(CPU_FREQ); Clocks::set_cpu_freq(CPU_FREQ);
IoPll::setup(1_000_000_000); IoPll::setup(1_000_000_000);