From eae21579bc350d252e93c7f40f3b57851f126ce7 Mon Sep 17 00:00:00 2001 From: newell Date: Wed, 4 Sep 2024 16:05:55 -0700 Subject: [PATCH] More updates. Fixed openocd. --- libboard_zynq/src/ddr/mod.rs | 3 ++- libboard_zynq/src/eth/mod.rs | 6 ++++-- openocd/ebaz4205.cfg | 2 +- szl/src/main.rs | 5 ++++- 4 files changed, 11 insertions(+), 5 deletions(-) diff --git a/libboard_zynq/src/ddr/mod.rs b/libboard_zynq/src/ddr/mod.rs index 3ae588e..9f57c37 100644 --- a/libboard_zynq/src/ddr/mod.rs +++ b/libboard_zynq/src/ddr/mod.rs @@ -478,11 +478,12 @@ impl DdrRam { let megabytes = 1023; #[cfg(any( feature = "target_coraz7", - feature = "target_ebaz4205", feature = "target_redpitaya", feature = "target_kasli_soc", ))] let megabytes = 512; + #[cfg(feature = "target_ebaz4205")] + let megabytes = 256; megabytes * 1024 * 1024 } diff --git a/libboard_zynq/src/eth/mod.rs b/libboard_zynq/src/eth/mod.rs index 8667533..9d0c0d6 100644 --- a/libboard_zynq/src/eth/mod.rs +++ b/libboard_zynq/src/eth/mod.rs @@ -154,6 +154,8 @@ pub struct Eth { impl Eth { pub fn eth0(macaddr: [u8; 6]) -> Self { + // EBAZ4205 ETH uses EMIO + #[cfg(not(feature = "target_ebaz4205"))] slcr::RegisterBlock::unlocked(|slcr| { // Manual example: 0x0000_1280 // MDIO @@ -511,7 +513,7 @@ impl PhyRst { }); Self::eth_reset_common(0xFFFF - 0x8000) } - + fn delay_ms(&mut self, ms: u64) { self.count_down.start(Milliseconds(ms)); nb::block!(self.count_down.wait()).unwrap(); @@ -531,7 +533,7 @@ impl PhyRst { self_.regs.gpio_direction.modify(|_, w| { w.phy_rst(true) }); - + self_ } diff --git a/openocd/ebaz4205.cfg b/openocd/ebaz4205.cfg index c1c0f08..db541f5 100644 --- a/openocd/ebaz4205.cfg +++ b/openocd/ebaz4205.cfg @@ -4,7 +4,7 @@ adapter driver ftdi ftdi vid_pid 0x0403 0x6010 ftdi channel 0 # Every pin set as high impedance except TCK, TDI, TDO and TMS -ftdi layout_init 0x0008 0x000b +ftdi layout_init 0x0088 0x008b # nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip) # This choice is arbitrary. Use other GPIO pin if desired. diff --git a/szl/src/main.rs b/szl/src/main.rs index aafda8b..fc91b7e 100644 --- a/szl/src/main.rs +++ b/szl/src/main.rs @@ -80,12 +80,15 @@ pub fn main_core0() { ); info!("Simple Zynq Loader starting..."); - #[cfg(not(feature = "target_kasli_soc"))] + #[cfg(not(any(feature = "target_kasli_soc", feature = "target_ebaz4205")))] const CPU_FREQ: u32 = 800_000_000; #[cfg(feature = "target_kasli_soc")] const CPU_FREQ: u32 = 1_000_000_000; + #[cfg(feature = "target_ebaz4205")] + const CPU_FREQ: u32 = 666_666_666; + ArmPll::setup(2 * CPU_FREQ); Clocks::set_cpu_freq(CPU_FREQ); IoPll::setup(1_000_000_000);