forked from M-Labs/zynq-rs
More updates. Fixed openocd.
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a75568bd42
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eae21579bc
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@ -478,11 +478,12 @@ impl DdrRam {
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let megabytes = 1023;
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let megabytes = 1023;
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#[cfg(any(
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#[cfg(any(
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feature = "target_coraz7",
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feature = "target_coraz7",
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feature = "target_ebaz4205",
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feature = "target_redpitaya",
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feature = "target_redpitaya",
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feature = "target_kasli_soc",
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feature = "target_kasli_soc",
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))]
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))]
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let megabytes = 512;
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let megabytes = 512;
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#[cfg(feature = "target_ebaz4205")]
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let megabytes = 256;
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megabytes * 1024 * 1024
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megabytes * 1024 * 1024
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}
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}
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@ -154,6 +154,8 @@ pub struct Eth<GEM: Gem, RX, TX> {
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impl Eth<Gem0, (), ()> {
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impl Eth<Gem0, (), ()> {
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pub fn eth0(macaddr: [u8; 6]) -> Self {
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pub fn eth0(macaddr: [u8; 6]) -> Self {
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// EBAZ4205 ETH uses EMIO
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#[cfg(not(feature = "target_ebaz4205"))]
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr::RegisterBlock::unlocked(|slcr| {
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// Manual example: 0x0000_1280
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// Manual example: 0x0000_1280
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// MDIO
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// MDIO
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@ -4,7 +4,7 @@ adapter driver ftdi
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ftdi vid_pid 0x0403 0x6010
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ftdi vid_pid 0x0403 0x6010
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ftdi channel 0
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ftdi channel 0
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# Every pin set as high impedance except TCK, TDI, TDO and TMS
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# Every pin set as high impedance except TCK, TDI, TDO and TMS
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ftdi layout_init 0x0008 0x000b
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ftdi layout_init 0x0088 0x008b
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# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
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# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
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# This choice is arbitrary. Use other GPIO pin if desired.
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# This choice is arbitrary. Use other GPIO pin if desired.
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@ -80,12 +80,15 @@ pub fn main_core0() {
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);
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);
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info!("Simple Zynq Loader starting...");
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info!("Simple Zynq Loader starting...");
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#[cfg(not(feature = "target_kasli_soc"))]
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#[cfg(not(any(feature = "target_kasli_soc", feature = "target_ebaz4205")))]
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const CPU_FREQ: u32 = 800_000_000;
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const CPU_FREQ: u32 = 800_000_000;
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#[cfg(feature = "target_kasli_soc")]
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#[cfg(feature = "target_kasli_soc")]
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const CPU_FREQ: u32 = 1_000_000_000;
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const CPU_FREQ: u32 = 1_000_000_000;
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#[cfg(feature = "target_ebaz4205")]
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const CPU_FREQ: u32 = 666_666_666;
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ArmPll::setup(2 * CPU_FREQ);
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ArmPll::setup(2 * CPU_FREQ);
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Clocks::set_cpu_freq(CPU_FREQ);
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Clocks::set_cpu_freq(CPU_FREQ);
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IoPll::setup(1_000_000_000);
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IoPll::setup(1_000_000_000);
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